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| full speed usb eprom mcu family c8051t620/621/320/321/322/323 rev. 1.1 2/11 copyright ? 2011 by silicon laboratories c8051t620/621/320/321/322/323 analog peripherals - 10-bit adc (?t620/320/321 only) ? up to 500 ksps ? up to 21 external inputs ? vref from on-chip vref, external pin, internal 1.8 v regulator or v dd ? internal or external start of conversion source ? built-in temperature sensor - comparators ? programmable hysteresis and response time ? configurable as interrupt or reset source ? low current (<0.5 a) usb function controller - usb specification 2.0 compliant - full speed (12 mbps) or low speed (1.5 mbps) oper- ation - integrated clock recovery; no external oscillator required for full speed or low speed - supports eight flexible endpoints - 1 kb usb buffer memory - integrated transceiver; no external resistors required on-chip debug - c8051f34a can be used as code development plat- form; complete development kit available - on-chip debug circuitry facilitates full speed, non- intrusive in-system debug - provides breakpoints, single stepping, ? inspect/modify memory and registers supply voltage 1.8 to 5.25 v - on-chip ldo for internal core supply - built-in supply voltage monitor high-speed 8051 c core - pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - up to 48 mips throughput with 48 mhz clock - expanded interrupt handler memory - 1280 bytes internal data ram (256 + 1024) - 16 kb byte-programmable eprom code memory - eprom can be programmed from firmware running on the device digital peripherals - 25 port i/o with high si nk current capability - hardware enhanced spi?, smbus?, and two enhanced uart serial ports - four general purpose 16-bit counter/timers - 16-bit programmable coun ter array (pca) with five capture/compare modules and enhanced pwm functionality clock sources - two internal oscillators: ? 48 mhz: 0.25% accuracy with clock recovery enabled. supports all usb and uart modes ? 80/40/20/10 khz low frequency, low power - external oscillator: crystal, rc, c, or cmos clock - can switch between clock s ources on-the-fly; useful in power saving modes package options: - 5 x 5 mm qfn28 or qfn32 - lqfp32 temperature range: ?40 to +85 c analog peripherals 16 kb eprom 1280 b sram por debug circuitry flexible interrupts 8051 cpu (48 mips) digital i/o 48 mhz precision internal oscillator high-speed controller core crossbar voltage comparators wdt uart1 smbus pca timer 0 timer 1 timer 2 timer 3 port 0 spi low frequency internal oscillator p3.0 ?t620/320/321 only 10-bit 500 ksps adc temp sensor a m u x vref port 1 port 2 usb controller / transceiver uart0 + - + -
c8051t620/621/320/321/322/323 2 rev. 1.1 rev. 1.1 3 c8051t620/621/320/321/322/323 table of contents 1. system overview ........ .................................................................................. ........... 15 2. ordering information ....... ............................................................................. ........... 20 3. pin definitions........... .................................................................................. ............. 21 4. lqfp-32 package specifi cations ............... ................................................. ........... 27 5. qfn-32 package specifications ..... ............................................................. ........... 29 6. qfn-28 package specifications ..... ............................................................. ........... 31 7. electrical characteristics ......... .................................................................. ............. 33 7.1. absolute maximum specificat ions................ .......................................... ........... 33 7.2. electrical characteri stics ................ ........................................................ ........... 34 7.3. typical performance curves ... ............................................................... ........... 42 8. 10-bit adc (adc0, c 8051t620/320/321 only)..... .......................................... ......... 43 8.1. output code formatting ....... .................................................................. ........... 44 8.2. 8-bit mode ....... ....................................................................................... ........... 44 8.3. modes of operation ... ............................................................................. ........... 44 8.3.1. starting a conversion...... ............................................................... ........... 44 8.3.2. tracking modes............... ............................................................... ........... 45 8.3.3. settling time requirement s................. .......................................... ........... 46 8.4. programmable window detector ............... ............................................. ........... 50 8.4.1. window detector example. ............... ............................................. ........... 52 8.5. adc0 analog multiplexe r (c8051t620/320/321 only)............ ................ ........... 53 9. temperature sensor (c8051t620/ 320/321 only) ....... ................................. ........... 55 9.1. calibration ..... ......................................................................................... ........... 56 10. voltage reference options ...... .................................................................. ........... 57 11. voltage regulators (reg0 and reg1)............ .......................................... ........... 59 11.1. voltage regulator (reg0)..... ............................................................... ........... 59 11.1.1. regulator mode selectio n............................................................ ........... 59 11.1.2. vbus detection ..... ...................................................................... ........... 59 11.2. voltage regulator (reg1)..... ............................................................... ........... 62 12. cip-51 microcontroller.............. .................................................................. ........... 64 12.1. instruction set....... ................................................................................ ........... 65 12.1.1. instruction and cpu timing ............... .......................................... ........... 65 12.2. cip-51 register descriptions .. ............................................................. ........... 70 13. prefetch engine......... .................................................................................. ........... 74 14. comparator0 and comparator1... ............... ............................................... ........... 75 14.1. comparator multiplexers .... .................................................................. ........... 82 15. memory organization .... ............................................................................. ........... 85 15.1. program memory....... ........................................................................... ........... 85 15.1.1. derivative id.... ............................................................................. ........... 86 15.1.2. temperature offset calibr ation............ .......................................... ......... 86 15.1.3. serialization..... ............................................................................. ........... 86 15.2. data memory ........... ............................................................................. ........... 87 15.2.1. internal ram ..... ........................................................................... ........... 87 15.2.1.1. general purpose regi sters ................ ................................. ........... 87 c8051t620/621/320/321/322/323 4 rev. 1.1 15.2.1.2. bit addressable locat ions ............. .............. ............... ........... ......... 87 15.2.1.3. stack ........... ...................................................................... ........... 87 15.2.2. external ram ..... ............... ........................................................... ........... 88 15.2.3. accessing usb fifo spac e ................ .......................................... ......... 88 16. special function registers...... .................................................................. ........... 91 17. interrupts ............ .................................................................................................... 9 6 17.1. mcu interrupt sour ces and vectors........... .......................................... ........... 96 17.1.1. interrupt priorities....... .................................................................. ........... 96 17.1.2. interrupt latency ............. ............................................................. ........... 97 17.2. interrupt register descripti ons .............. ............................................... ........... 97 17.3. int0 and int1 external interrupt sources ............ ............................... ......... 105 18. program memory (eprom)...... .................................................................. ......... 107 18.1. programming the epr om memory......... ............................................. ......... 107 18.1.1. eprom programming over the c2 interface............ ................. ........... 107 18.1.2. eprom in-application pr ogramming............ ............................... ......... 108 18.2. security options ...... ............................................................................. ......... 109 18.3. eprom writing guidelines ..... ............................................................. ......... 109 18.3.1. vdd maintenance and t he vdd monitor ...... ............................... ......... 109 18.3.2. pswe maintenance ............. ........................................................ ......... 110 18.3.3. system clock ...... ......................................................................... ......... 110 18.4. program memory crc .......... ............................................................... ......... 110 18.4.1. performing 32-bit crcs on full eprom content .... ................. ........... 110 18.4.2. performing 16-bit crcs on 256-byte eprom blocks........ .................. 110 19. power management modes...... .................................................................. ......... 113 19.1. idle mode....... ....................................................................................... ......... 113 19.2. stop mode ............... ............................................................................. ......... 114 19.3. suspend mode .......... ........................................................................... ......... 114 20. reset sources ........... .................................................................................. ......... 116 20.1. power-on reset ...... ............................................................................. ......... 117 20.2. power-fail reset / vdd moni tor .................... .............. ............... .................. 117 20.3. external reset ................ ...................................................................... ......... 119 20.4. missing clock detector reset . ............................................................. ......... 119 20.5. comparator0 reset ............ .................................................................. ......... 119 20.6. pca watchdog timer reset ..... ........................................................... ......... 120 20.7. eprom error reset ... ............... ........................................................... ......... 120 20.8. software reset ........ ............................................................................. ......... 120 20.9. usb reset............... ............................................................................. ......... 120 21. oscillators and clock selection ............ .................................................. ........... 122 21.1. system clock selection...... .................................................................. ......... 123 21.2. usb clock selection ............. ............................................................... ......... 123 21.3. programmable internal high-frequency (h-f) oscillator .. ................. ........... 125 21.3.1. internal oscillator sus pend mode ............... ................................. ......... 125 21.4. clock multiplier ..... ................................................................................ ......... 127 21.5. programmable internal lo w-frequency (l-f) oscillator ... ................. ........... 128 21.5.1. calibrating the internal l-f oscillator........ ................................. ........... 128 rev. 1.1 5 c8051t620/621/320/321/322/323 21.6. external oscillator drive circuit........ .................................................. ........... 129 21.6.1. external crystal mode.................................................................. ......... 129 21.6.2. external rc example...... ............................................................. ......... 131 21.6.3. external capacitor exam ple............... .......................................... ......... 131 22. port input/output ...... .................................................................................. ......... 133 22.1. port i/o modes of operation. ................... ............................................. ......... 134 22.1.1. port pins configured fo r analog i/o.......... ................................. ........... 134 22.1.2. port pins configured fo r digital i/o.......... ................................. ........... 134 22.1.3. interfacing port i/o to 5v logic .............. .............. ............... .................. 135 22.2. assigning port i/ o pins to analog and digital functi ons................. .............. 135 22.2.1. assigning port i/o pins to analog f unctions ............ ................. ........... 135 22.2.2. assigning port i/o pins to digital f unctions............ ............ .................. 135 22.2.3. assigning port i/o pins to external digital event capture functions ... 136 22.3. priority crossbar decoder .. .................................................................. ......... 137 22.4. port i/o initializatio n ................ ............................................................. ......... 141 22.5. port match ............ ................................................................................ ......... 144 22.6. special function regist ers for accessing an d configuring port i/o ............. 146 23. universal serial bus controll er (usb0) .............. .............. ............... .................. 155 23.1. endpoint addressing .......... .................................................................. ......... 155 23.2. usb transceiver ..... ............................................................................. ......... 156 23.3. usb register access ......... .................................................................. ......... 158 23.4. usb clock configuration....... ............................................................... ......... 162 23.5. fifo management ......... ...................................................................... ......... 163 23.5.1. fifo split mode .. ......................................................................... ......... 164 23.5.2. fifo double buffering ..... ............... ............................................. ......... 164 23.5.1. fifo access ....... ......................................................................... ......... 165 23.6. function addressing ............................................................................. ......... 166 23.7. function configurat ion and control............ .......................................... ......... 166 23.8. interrupts ....... ....................................................................................... ......... 169 23.9. the serial interface engine .................................................................. ......... 175 23.10. endpoint0 .............. ............................................................................. ......... 175 23.10.1. endpoint0 setup transa ctions ............... ................................. ......... 176 23.10.2. endpoint0 in transactions ................. ................................................. 176 23.10.3. endpoint0 out transacti ons............... .............. ............... .................. 177 23.11. configuring e ndpoints1-3 ........... ........................................................ ......... 179 23.12. controlling end points1-3 in................. ................ ............................... ......... 180 23.12.1. endpoints1-3 in interr upt or bulk mode.... ................................. ......... 180 23.12.2. endpoints1-3 in isoc hronous mode.......... ................................. ......... 181 23.13. controlling en dpoints1-3 out............. ............................................... ......... 183 23.13.1. endpoints1-3 out inte rrupt or bulk mode............ ............ .................. 184 23.13.2. endpoints1-3 out isochronous mode. .............. ............... .................. 184 24. smbus................. ......................................................................................... ......... 188 24.1. supporting document s ......................................................................... ......... 189 24.2. smbus configuration.......... .................................................................. ......... 189 24.3. smbus operation ...... ........................................................................... ......... 189 c8051t620/621/320/321/322/323 6 rev. 1.1 24.3.1. transmitter vs. receiver.. ............... ............................................. ......... 190 24.3.2. arbitration........ ............................................................................. ......... 190 24.3.3. clock low extensio n................ .................................................. ........... 190 24.3.4. scl low timeout... ...................................................................... ......... 190 24.3.5. scl high (smbus free) timeout ............... ................................. ......... 191 24.4. using the smbus..... ............................................................................. ......... 191 24.4.1. smbus configuration regi ster............. ................................................. 191 24.4.2. smb0cn control register ........................................................... ......... 195 24.4.2.1. software ack generat ion .................. ................................. ......... 195 24.4.2.2. hardware ack generat ion ............... ................................. ........... 195 24.4.3. hardware slave addre ss recognition ........ ................................. ......... 197 24.4.4. data register .... ........................................................................... ......... 200 24.5. smbus transfer modes......... ............................................................... ......... 201 24.5.1. write sequence (master) .. ........................................................... ......... 201 24.5.2. read sequence (master) ..... ........................................................ ......... 202 24.5.3. write sequence (slave) ... ............... ............................................. ......... 203 24.5.4. read sequence (slave) .... ........................................................... ......... 204 24.6. smbus status decodi ng................... ................. ................................. ........... 204 25. uart0 ................. ......................................................................................... ......... 209 25.1. enhanced baud rate generati on............ ............................................. ......... 210 25.2. operational modes ............. .................................................................. ......... 211 25.2.1. 8-bit uart ........ ........................................................................... ......... 211 25.2.2. 9-bit uart ........ ........................................................................... ......... 212 25.3. multiprocessor communication s ................ .......................................... ......... 213 26. uart1 ................. ......................................................................................... ......... 217 26.1. baud rate generator ........................................................................... ......... 217 26.2. data format.......... ................................................................................ ......... 218 26.3. configuration and o peration ............... ................................................. ......... 219 26.3.1. data transmission .......... ............................................................. ......... 220 26.3.2. data reception ... ......................................................................... ......... 220 26.3.3. multiprocessor communicat ions ................. ................................. ......... 221 27. enhanced serial peripheral in terface (spi0) ......... ................................. ........... 227 27.1. signal descriptions.. ............................................................................. ......... 228 27.1.1. master out, slave in (m osi).............. .............. ............................ ......... 228 27.1.2. master in, slave out (m iso).............. .......................................... ......... 228 27.1.3. serial clock (sck ) ................................................................................ 228 27.1.4. slave select (nss) ....... ............................................................... ......... 228 27.2. spi0 master mode op eration .............. ................................................. ......... 228 27.3. spi0 slave m ode operation .................. ............................................... ......... 230 27.4. spi0 interrupt sources ....... .................................................................. ......... 231 27.5. serial clock phase and polari ty .............. ............................................. ......... 231 27.6. spi special function register s ............................................................ ......... 233 28. timers ................... .................................................................................. .............. 24 0 28.1. timer 0 and timer 1 ... ............... ........................................................... ......... 242 28.1.1. mode 0: 13-bit counter/timer ............ .......................................... ......... 242 rev. 1.1 7 c8051t620/621/320/321/322/323 28.1.2. mode 1: 16-bit counter/timer ............ .......................................... ......... 243 28.1.3. mode 2: 8-bit counter/timer with auto-reload.... ............... .................. 243 28.1.4. mode 3: two 8-bit co unter/timers (timer 0 only)... ............................. 244 28.2. timer 2 .......... ....................................................................................... ......... 250 28.2.1. 16-bit timer with auto-rel oad................ .............. ............... .................. 250 28.2.2. 8-bit timers with auto -reload...................................................... ......... 251 28.2.3. low-frequency oscillator (lfo) captur e mode ................. .................. 252 28.3. timer 3 .......... ....................................................................................... ......... 256 28.3.1. 16-bit timer with auto-rel oad................ .............. ............... .................. 256 28.3.2. 8-bit timers with auto -reload...................................................... ......... 257 28.3.3. low-frequency oscillator (lfo) captur e mode ................. .................. 258 29. programmable counter array............ ........................................................ ......... 262 29.1. pca counter/timer ............ .................................................................. ......... 263 29.2. pca0 interrupt sources...... .................................................................. ......... 264 29.3. capture/compare modules ..... ............................................................. ......... 265 29.3.1. edge-triggered capture m ode.............................. ............... .................. 266 29.3.2. software timer (compare) mode................ ................................. ......... 267 29.3.3. high-speed output mode ............... ............................................. ......... 268 29.3.4. frequency output mode ............... ................ ............................... ......... 269 29.3.5. 8-bit, 9-bit, 10-bit and 11-bit pulse width modula tor modes ................. 270 29.3.5.1. 8-bit pulse width mo dulator mode........ ............................... ......... 270 29.3.5.2. 9/10/11-bit pulse wi dth modulator mode.......... ................. ........... 271 29.3.6. 16-bit pulse width modul ator mode....... .............. ............... .................. 272 29.4. watchdog timer mode ... ...................................................................... ......... 273 29.4.1. watchdog timer o peration .................. ................................................. 273 29.4.2. watchdog timer usage ....... ........................................................ ......... 274 29.5. register descriptions for pc a0............. ............................................... ......... 275 30. c2 interface ............. .................................................................................. ........... 282 30.1. c2 interface registers........ .................................................................. ......... 282 30.2. c2 pin sharing ........ ............................................................................. ......... 289 document change list............... ...................................................................... ......... 290 contact information.......... ................................................................................ ......... 292 c8051t620/621/320/321/322/323 8 rev. 1.1 list of figures figure 1.1. c8051t620/1 block di agram ........... .......................................... ........... 16 figure 1.2. c8051t320/2 block di agram ........... .......................................... ........... 17 figure 1.3. c8051t321/3 block di agram ........... .......................................... ........... 18 figure 1.4. typical bus-power ed connections ......... ................................. ............. 19 figure 3.1. qfn-32 pinout diagr am (top view) ......... ................................. ........... 24 figure 3.2. lqfp-32 pi nout diagram (top view) ............. ............................ ........... 25 figure 3.3. qfn-28 pinout diagr am (top view) ......... ................................. ........... 26 figure 4.1. lqfp-32 package draw ing .............. .......................................... ........... 27 figure 4.2. lqfp-32 recommended pcb land pattern .......... ................. ............. 28 figure 5.1. qfn-32 package drawin g ...................... ................................. ............. 29 figure 5.2. qfn-32 recomm ended pcb land pattern ............ ................. ............. 30 figure 6.1. qfn-28 package drawin g ...................... ................................. ............. 31 figure 6.2. qfn-28 recomm ended pcb land pattern ............ ................. ............. 32 figure 7.1. normal mode digital supply current vs. frequency (m pce = 1) ......... 42 figure 7.2. idle mode digital supply current vs. frequency (mpce = 1) .. ............. 42 figure 8.1. adc0 functional blo ck diagram ............. ................................. ............. 43 figure 8.2. 10-bit adc track and conversion exampl e timing ........... ............ ...... 45 figure 8.3. adc0 equivalent i nput circuits ............ .............. ............... ........... ......... 46 figure 8.4. adc window compar e example: right-justified da ta ............ ............. 52 figure 8.5. adc window compar e example: left-justified data .............. ............. 52 figure 8.6. adc0 multiplexer bl ock diagram ............ ................................. ............. 53 figure 9.1. temperature sensor trans fer function ............. ............... ........... ......... 55 figure 9.2. toffh and toffl ca libration value orie ntation .............. ............ ...... 56 figure 9.3. temperature sens or error with 1-point calibra tion at 0 celsius ........... 56 figure 10.1. voltage re ference functional blo ck diagram .............. .............. ......... 57 figure 11.1. reg0 configuratio n: usb bus-powered ................................. ........... 59 figure 11.2. reg0 configuratio n: usb self-powered ............ ............ ........... ......... 60 figure 11.3. reg0 configurat ion: usb self-power ed, regulator disabled ............ 60 figure 11.4. reg0 configuratio n: no usb connection .......... ............ ........... ......... 61 figure 12.1. cip-51 block diagram ............... ............................................... ........... 64 figure 14.1. comparator0 functi onal block diagram ............. ............ ........... ......... 75 figure 14.2. comparator1 functi onal block diagram ............. ............ ........... ......... 76 figure 14.3. comparator hysteres is plot ........ ............................................. ........... 77 figure 14.4. comparator input multiplexer block diagram ...... ............ ........... ......... 82 figure 15.1. memory map .......... .................................................................. ........... 85 figure 15.2. program memory map ............... ............................................... ........... 86 figure 15.3. usb fifo space and xram me mory map with usbfae set to 1 ..... 89 figure 20.1. reset sources ........ .................................................................. ......... 116 figure 20.2. power-on and v dd monitor reset timing ..................... .................. 117 figure 21.1. oscillator options .. ............... .................................................. ........... 122 figure 21.2. external crystal ex ample ................... .............. ............... .................. 130 figure 22.1. port i/o f unctional block diagram ............... ............................ ......... 133 figure 22.2. port i/o cell block diagram ........ ............................................. ......... 134 rev. 1.1 9 c8051t620/621/320/321/322/323 figure 22.3. priority crossbar decoder potential pin assign ments ........... ........... 138 figure 22.4. priority crossb ar decoder example 1?no skip ped pins ................. 139 figure 22.5. priority crossbar decoder example 2?skipping pins ........... ........... 140 figure 23.1. usb0 block diagram ................... ............................................. ......... 155 figure 23.2. usb0 register a ccess scheme .............. ................................. ......... 158 figure 23.3. usb fifo allocation ................... ............................................. ......... 164 figure 24.1. smbus block diagram ............................................................. ......... 188 figure 24.2. typical smbus confi guration ................ ................................. ........... 189 figure 24.3. smbus transaction ..... ............................................................. ......... 190 figure 24.4. typical smbus scl generation .............. ................................. ......... 192 figure 24.5. typical master wr ite sequence .............. ................................. ......... 201 figure 24.6. typical ma ster read sequence ....... ................................................. 202 figure 24.7. typical sl ave write sequence .. ............................................... ......... 203 figure 24.8. typical slave read sequence ................ ................................. ......... 204 figure 25.1. uart0 block diagram ............................................................. ......... 209 figure 25.2. uart0 baud rate logic ................ .......................................... ......... 210 figure 25.3. uart interconnect di agram ............ ................................................. 211 figure 25.4. 8-bit uart timing diagram ........... .......................................... ......... 211 figure 25.5. 9-bit uart timing diagram ........... .......................................... ......... 212 figure 25.6. uart multi-proc essor mode interconne ct diagram ......... ................ 213 figure 26.1. uart1 block diagram ............................................................. ......... 217 figure 26.2. uart1 timing without parity or extra bit .... ............................ ......... 219 figure 26.3. uart1 timing with parity .......... ............................................. ......... 219 figure 26.4. uart1 timing with extra bit ............. .............. ............... .................. 219 figure 26.5. typical uart inte rconnect diagram ................... ............ .................. 220 figure 26.6. uart multi-proc essor mode interconne ct diagram ......... ................ 221 figure 27.1. spi block di agram ............... .................................................. ........... 227 figure 27.2. multiple-master mode connection diagram ........ ............ .................. 229 figure 27.3. 3-wire single master and 3-wire single slave mode ? connection diagram ............. .................................................. ........... 229 figure 27.4. 4-wire single master mode and 4-wire slave mode ? connection diagram ............. .................................................. ........... 230 figure 27.5. master mode data/ clock timing ............. ................................. ......... 232 figure 27.6. slave mode data/clock timing (ckpha = 0) .. ............... .................. 232 figure 27.7. slave mode data/clock timing (ckpha = 1) .. ............... .................. 233 figure 27.8. spi master timing (ckpha = 0) .... .......................................... ......... 237 figure 27.9. spi master timing (ckpha = 1) .... .......................................... ......... 237 figure 27.10. spi slave timing (c kpha = 0) ............. ................................. ......... 238 figure 27.11. spi slave timing (c kpha = 1) ............. ................................. ......... 238 figure 28.1. t0 mode 0 bl ock diagram .............. .............. ............................ ......... 243 figure 28.2. t0 mode 2 bl ock diagram .............. .......................................... ......... 244 figure 28.3. t0 mode 3 bl ock diagram .............. .......................................... ......... 245 figure 28.4. timer 2 16-bit mode block diagram ....... ................................. ......... 250 figure 28.5. timer 2 8-bit mode block diagram ....... ................................. ........... 251 c8051t620/621/320/321/322/323 10 rev. 1.1 figure 28.6. timer 2 low-f requency oscillati on capture mode blo ck diagram ... 252 figure 28.7. timer 3 16-bit mode block diagram ....... ................................. ......... 256 figure 28.8. timer 3 8-bit mode block diagram ....... ................................. ........... 257 figure 28.9. timer 3 low-f requency oscillati on capture mode blo ck diagram ... 258 figure 29.1. pca block diagram ... ............................................................... ......... 262 figure 29.2. pca counter/timer block diagram ......... ................................. ......... 264 figure 29.3. pca interrupt block diagram ................ ................................. ........... 265 figure 29.4. pca capture mode dia gram ............ ................................................. 267 figure 29.5. pca software time r mode diagram ....... ................................. ......... 268 figure 29.6. pca high-speed out put mode diagram ... ............................... ......... 269 figure 29.7. pca frequen cy output mode .......... ................................................. 270 figure 29.8. pca 8-bit pwm mode diagram ......... .............. ............... .................. 271 figure 29.9. pca 9, 10 and 11-bi t pwm mode diagram .......... ................. ........... 272 figure 29.10. pca 16-bit pwm mode ................ .......................................... ......... 273 figure 29.11. pca module 2 wi th watchdog timer enabled .... ................. ........... 274 figure 30.1. typical c2 pin shar ing ................ ............................................. ......... 289 rev. 1.1 11 c8051t620/621/320/321/322/323 list of registers sfr definition 8.1. adc0cf: adc0 configuration ........ ................................. ............. 47 sfr definition 8.2. adc0h: adc0 data word msb ...... ................................. ............. 48 sfr definition 8.3. adc0l: adc0 data word lsb ............... ............................ ........... 48 sfr definition 8.4. adc0cn : adc0 control ........... .......................................... ........... 49 sfr definition 8.5. adc0gth: adc0 greater-than da ta high byte ...... ........... ......... 50 sfr definition 8.6. adc0gtl: adc0 greater-than data low byte ............... ............. 50 sfr definition 8.7. adc0lth: adc0 less-than data high byte ............ ........... ......... 51 sfr definition 8.8. adc0ltl: ad c0 less-than data low byte .. ...................... ......... 51 sfr definition 8.9. amx0p: amux 0 positive channel select ..... ............ ........... ......... 54 sfr definition 10.1. ref0cn: refe rence control ......... ................................. ............. 58 sfr definition 11.1. reg0 1cn: voltage regulator c ontrol ................. .............. ......... 63 sfr definition 12.1. dpl: data po inter low byte ....... .............. ............... ........... ......... 71 sfr definition 12.2. dph: data pointer high byte .. .......................................... ........... 71 sfr definition 12.3. sp: st ack pointer ........ ........................................................ ......... 72 sfr definition 12.4. acc: accumulator ........ .................................................. ............. 72 sfr definition 12.5. b: b r egister ............. ........................................................ ........... 72 sfr definition 12.6. psw: program status word .......... ................................. ............. 73 sfr definition 13.1. pfe0 cn: prefetch engine control ......... ............................ ......... 74 sfr definition 14.1. cpt0 cn: comparator0 control .............. ............................ ......... 78 sfr definition 14.2. cpt0md: co mparator0 mode selection ....... ................. ............. 79 sfr definition 14.3. cpt1 cn: comparator1 control .............. ............................ ......... 80 sfr definition 14.4. cpt1md: co mparator1 mode selection ....... ................. ............. 81 sfr definition 14.5. cpt0mx: co mparator0 mux selection ...... ............ ........... ......... 83 sfr definition 14.6. cpt1mx: co mparator1 mux selection ...... ............ ........... ......... 84 sfr definition 15.1. emi0 cn: external memory interface co ntrol .............. ................ 88 sfr definition 15.2. emi0 cf: external memory configuration ........................... ......... 90 sfr definition 17.1. ie: in terrupt enable .............. ............................................. ........... 99 sfr definition 17.2. ip: inte rrupt priority ............ ............................................... ......... 100 sfr definition 17.3. eie1 : extended interrupt enable 1 ......... ................................... 101 sfr definition 17.4. eip1 : extended interrupt priority 1 ....... ............................ ......... 102 sfr definition 17.5. eie2 : extended interrupt enable 2 ......... ................................... 103 sfr definition 17.6. eip2 : extended interrupt priority 2 ....... ............................ ......... 104 sfr definition 17.7. it01cf: int0 /int1 configurationo .......... ............... .................. 106 sfr definition 18.1. psctl: prog ram store r/w control ................................ ......... 111 sfr definition 18.2. memkey: epr om memory lock and key ... ................. ........... 111 sfr definition 18.3. iapcn: in-application programming contro l ............... .............. 112 sfr definition 19.1. pcon: power control ............. .......................................... ......... 115 sfr definition 20.1. vdm0 cn: vdd monitor control ................................................ 119 sfr definition 20.2. rstsrc : reset source ......... .......................................... ......... 121 sfr definition 21.1. clksel: clock select ............ .......................................... ......... 124 sfr definition 21.2. oscicl: inte rnal h-f oscillator calibrati on ................ .............. 125 sfr definition 21.3. oscicn: inte rnal h-f oscillator con trol .. ............... .................. 126 sfr definition 21.4. clkmul : clock multiplier control ........ ............................ ......... 127 c8051t620/621/320/321/322/323 12 rev. 1.1 sfr definition 21.5. osclcn: inte rnal l-f oscillator control ..... ............ .................. 128 sfr definition 21.6. oscx cn: external oscillator control ................. .............. ......... 132 sfr definition 22.1. xbr0: port i/o crossbar register 0 ..... ............................ ......... 142 sfr definition 22.2. xbr1: port i/o crossbar register 1 ..... ............................ ......... 143 sfr definition 22.3. xbr2: port i/o crossbar register 2 ..... ............................ ......... 144 sfr definition 22.4. p0mask: port 0 mask register ..... ................................. ........... 145 sfr definition 22.5. p0mat: port 0 match register ... .............. ............... .................. 145 sfr definition 22.6. p1mask: port 1 mask register ..... ................................. ........... 146 sfr definition 22.7. p1mat: port 1 match register ... .............. ............... .................. 146 sfr definition 22.8. p0: port 0 .... ...................................................................... ......... 147 sfr definition 22.9. p0mdin: port 0 input mode ........... ................................. ........... 148 sfr definition 22.10. p0md out: port 0 output mode ........... ................................... 148 sfr definition 22.11. p0skip: port 0 skip ........... ............................................. ......... 149 sfr definition 22.12. p1: port 1 .... .................................................................. ........... 149 sfr definition 22.13. p1mdin: port 1 input mode ......... ................................. ........... 150 sfr definition 22.14. p1md out: port 1 output mode ........... ................................... 150 sfr definition 22.15. p1skip: port 1 skip ........... ............................................. ......... 151 sfr definition 22.16. p2: port 2 .... .................................................................. ........... 151 sfr definition 22.17. p2mdin: port 2 input mode ......... ................................. ........... 152 sfr definition 22.18. p2md out: port 2 output mode ........... ................................... 152 sfr definition 22.19. p2skip: port 2 skip ........... ............................................. ......... 153 sfr definition 22.20. p3: port 3 .... .................................................................. ........... 153 sfr definition 22.21. p3md out: port 3 output mode ........... ................................... 154 sfr definition 23.1. usb0 xcn: usb0 transceiver control ................. ..................... 157 sfr definition 23.2. usb0 adr: usb0 indirect ad dress .......... ............... .................. 159 sfr definition 23.3. usb0da t: usb0 data ........... .......................................... ......... 160 sfr definition 24.1. smb0cf: smbu s clock/configuration ........ ............ .................. 194 sfr definition 24.2. smb0cn: smbu s control .............. ................................. ........... 196 sfr definition 24.3. smb0 adr: smbus slave address ......... ................................... 198 sfr definition 24.4. smb0adm: smbus slave address mask .... ............ .................. 199 sfr definition 24.5. smb0dat: smbu s data ................ ................................. ........... 200 sfr definition 25.1. scon0: serial port 0 control ..... .............. ............... .................. 214 sfr definition 25.2. sbuf0: seri al (uart0) port data buffer . ............... .................. 215 sfr definition 26.1. scon1: uart1 control ......... .......................................... ......... 222 sfr definition 26.2. smod 1: uart1 mode ........... .......................................... ......... 223 sfr definition 26.3. sbuf1: uart1 data buffer ... .......................................... ......... 224 sfr definition 26.4. sbcon1: ua rt1 baud rate generator cont rol ........... ........... 225 sfr definition 26.5. sbrlh1: uart1 baud rate generator high byte .. ................. 225 sfr definition 26.6. sbrll1: ua rt1 baud rate generator low byte .......... ........... 226 sfr definition 27.1. spi0cfg: spi 0 configuration ....... ................ ................. ........... 234 sfr definition 27.2. spi0cn : spi0 control ............ .......................................... ......... 235 sfr definition 27.3. spi0ckr: spi 0 clock rate ........... ................................. ........... 236 sfr definition 27.4. spi0dat: spi0 data ........... ............................................. ......... 236 sfr definition 28.1. ckcon: clock control ........... .......................................... ......... 241 rev. 1.1 13 c8051t620/621/320/321/322/323 sfr definition 28.2. tcon: timer c ontrol .............. .......................................... ......... 246 sfr definition 28.3. tmod: timer m ode ................ .......................................... ......... 247 sfr definition 28.4. tl0: timer 0 low byte ......... ............................................. ......... 248 sfr definition 28.5. tl1: timer 1 low byte ......... ............................................. ......... 248 sfr definition 28.6. th0: timer 0 high byte .............. .............. ............... .................. 249 sfr definition 28.7. th1: timer 1 high byte .............. .............. ............... .................. 249 sfr definition 28.8. tmr2cn: timer 2 control ............. ................................. ........... 253 sfr definition 28.9. tmr2rll: ti mer 2 reload register low byte ............... ........... 254 sfr definition 28.10. tmr2 rlh: timer 2 reload register high byte . ..................... 254 sfr definition 28.11. tmr2l: timer 2 low byte .... .......................................... ......... 254 sfr definition 28.12. tmr2h timer 2 high byte ........... ................................. ........... 255 sfr definition 28.13. tmr3 cn: timer 3 control .... .......................................... ......... 259 sfr definition 28.14. tmr3 rll: timer 3 reload re gister low byte ... ..................... 260 sfr definition 28.15. tmr3 rlh: timer 3 reload register high byte . ..................... 260 sfr definition 28.16. tmr3l: timer 3 low byte .... .......................................... ......... 260 sfr definition 28.17. tmr3h timer 3 high byte ........... ................................. ........... 261 sfr definition 29.1. pca0cn : pca control ........... .......................................... ......... 276 sfr definition 29.2. pca0md: pca mo de ............. .......................................... ......... 277 sfr definition 29.3. pca0pwm: pca pwm configuration ......... ............ .................. 278 sfr definition 29.4. pca0cpmn : pca capture/compare mode .. ................. ........... 279 sfr definition 29.5. pca 0l: pca counter/timer low byte ................. ..................... 280 sfr definition 29.6. pca0h: pca counter/timer high byte ....... ............ .................. 280 sfr definition 29.7. pca0cpln: pca capture module low byte . ................. ........... 281 sfr definition 29.8. pca0cphn: pca capture module high byte ................ ........... 281 c8051t620/621/320/321/322/323 14 rev. 1.1 list of tables table 2.1. product select ion guide ................. ............................................. ........... 20 table 3.1. pin definitions for the c8051t620/ 621/320/321/322/323 ....... ................ 21 table 7.1. absolute maximum rati ngs ................... .............. ............... ........... ......... 33 table 7.2. global electrical char acteristics ............ .............. ............... ........... ......... 34 table 7.3. port i/ o dc electrical char acteristics ......... ................................. ........... 35 table 7.4. reset electric al characteristics ...... ............................................. ........... 35 table 7.5. internal voltage regulator electrical characteristi cs ................ ............. 36 table 7.6. eprom el ectrical characteristics ............................................... ........... 36 table 7.7. internal high-frequency oscillator electrical char acteristics .... ............. 37 table 7.8. internal low-frequen cy oscillator electrical char acteristics .... ............. 37 table 7.9. external oscillator electrical characteristics ....... ............... ........... ......... 37 table 7.10. adc0 electric al characteristics ....... .......................................... ........... 38 table 7.11. temperature sensor electrical char acteristics ............. .............. ......... 39 table 7.12. voltage reference elec trical characteristics ....... ............ ........... ......... 39 table 7.13. comparator electrical characteristics .... ................................. ............. 40 table 7.14. usb transceiver elec trical characteristics .......... ............ ........... ......... 41 table 12.1. cip-51 instruction set summary ............ ................................. ............. 66 table 16.1. special func tion register (sfr) memory map . ............... ........... ......... 91 table 16.2. special functi on registers .............. .......................................... ........... 92 table 17.1. interrupt summ ary ................. .................................................. ............. 98 table 18.1. security byte decodi ng .............. ............................................... ......... 109 table 23.1. endpoint addr essing scheme ............. .............. ............... .................. 156 table 23.2. usb0 c ontroller registers ......... ............................................... ......... 161 table 23.3. fifo configur ations .............. .................................................. ........... 165 table 26.1. baud rate generator settings for st andard baud rates ................... 218 table 29.1. pca timebase input op tions ............ ................................................. 263 table 29.2. pca0cpm and pca0 pwm bit settings for pca ? capture/compare modules ... .................................................. ........... 266 rev. 1.1 15 c8051t620/621/320/321/322/323 1. system overview c8051t620/621/320/321/322/323 devic es are fully integrated mixed- signal system-on-a-chip mcus. highlighted features are listed below. refer to table 2.1 for specific product feature selection and part ordering numbers. ? high-speed pipelined 8051-compatible microcontroller core (up to 48 mips) ? in-system, full-speed, non-intrusive debug interface (on-chip) ? c8051f34a isp flash device is available for quick in-system code development ? universal serial bus (usb) function controller wit h eight flexible endpoint pipes, integrated transceiver, and 1 kb fifo ram ? supply voltage regulator ? 10-bit 500 ksps single-ended adc with analog multiplexer and integrated temperature sensor ? precision calibrated 48 mhz internal oscillator ? internal low-frequency oscillato r for additional power savings ? 16 kb of on-chip byte-programmable eprom ? (512 bytes are reserved) ? 1280 bytes of on-chip ram (256 + 1 kb) ? smbus/i2c, 2 uarts, and enhanced spi serial interfaces implemented in hardware ? four general-purpose 16-bit timers ? programmable counter/timer array (pca) with five capture/compare modules and watchdog timer function ? on-chip power-on reset, v dd monitor, and temperature sensor ? on-chip voltage comparators (2) ? up to 25 port i/o with on-chip power-on reset, v dd monitor, watchdog timer, and clock oscillator, the c8051t620/621/320/321/322/323 devices are truly stand -alone system-on-a-chip solutions. user soft- ware has complete control of all peripherals, and ma y individually shut down any or all peripherals for power savings. code written for the c8051t620/621 /320/321/322/ 323 family of processors will run on the c8051f34a mixed-signal isp flash microcontroller, providing a quick, cost-effective way to develop code without requiring special emulator circui try. the c8051t620 /621/320/32 1/322/323 processors include silicon lab- oratories? 2-wire c2 debug and programming interf ace, which allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection of memory, viewing and modification of special f unction registers, setting breakpoints, single stepping, run and halt commands. all analog and digital peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user func tions, allowing in-system debugging without occupying package pins. each device is specified for 1.8-to-5.25 v operation ov er the industrial temperature range (?40 to +85 c). for voltages above 3.6 v, the on-chip voltage regulator must be used. a minimum of 3.0 v is required for usb communication. an additional internal ldo is used to supply the processor core voltage at 1.8 v. the port i/o and rst pins are tolerant of input signals up to 5 v. the c8051t620/1 are available in 32-pin qfn packaging, the c8051t320/2 are available in 32-pin lq fp packaging, and the c8051t321/3 are available in 28-pin qfn packaging. see table 2.1 for ordering in formation. a block diagram is shown in figure 1.1. c8051t620/621/320/321/322/323 16 rev. 1.1 figure 1.1. c8051t620/1 block diagram digital peripherals uart0 timers 0, 1, 2, 3 pca/ wdt smbus priority crossbar decoder p0.0 p0.1 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7/vref crossbar control port i/o configuration sfr bus p1.0 p1.1 p1.2 p1.3 p1.4 p1.5/vpp p3.0/c2d spi debug / programming hardware power on reset reset c2d c2ck/rst p1.6 p1.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 usb peripheral controller 1k byte ram full / low speed transceiver cip-51 8051 controller core 16k byte otp program memory 256 byte sram 1024 byte xram d+ d- vbus uart1 vio port 0 drivers port 1 drivers port 3 drivers port 2 drivers voltage regulator regulator core power peripheral power gnd regin vdd in-system programming hardware vpp system clock setup external oscillator internal oscillator low freq. oscillator clock recovery xtal1 xtal2 analog peripherals (c8051t620) 2 comparators + - 10-bit 500ksps adc a m u x temp sensor vref vdd vdd vref gnd cp0, cp0a voltage reference vref + - cp1, cp1a rev. 1.1 17 c8051t620/621/320/321/322/323 figure 1.2. c8051t320/2 block diagram digital peripherals uart0 timers 0, 1, 2, 3 pca/ wdt smbus priority crossbar decoder p0.0 p0.1 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7/vref crossbar control port i/o configuration sfr bus p1.0 p1.1 p1.2 p1.3 p1.4 p1.5/vpp p3.0/c2d spi debug / programming hardware power on reset reset c2d c2ck/rst p1.6 p1.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 usb peripheral controller 1k byte ram full / low speed transceiver cip-51 8051 controller core 16k byte otp program memory 256 byte sram 1024 byte xram d+ d- vbus uart1 port 0 drivers port 1 drivers port 3 drivers port 2 drivers voltage regulator regulator core power peripheral power gnd regin vdd in-system programming hardware vpp system clock setup external oscillator internal oscillator low freq. oscillator clock recovery xtal1 xtal2 p2.7 analog peripherals (c8051t320) 2 comparators + - 10-bit 500ksps adc a m u x temp sensor vref vdd vdd vref gnd cp0, cp0a voltage reference vref + - cp1, cp1a c8051t620/621/320/321/322/323 18 rev. 1.1 figure 1.3. c8051t321/3 block diagram digital peripherals uart0 timers 0, 1, 2, 3 pca/ wdt smbus priority crossbar decoder p0.0 p0.1 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7/vref crossbar control port i/o configuration sfr bus p1.0 p1.1 p1.2 p1.3 p1.4 p1.5/vpp p3.0/c2d spi debug / programming hardware power on reset reset c2d c2ck/rst p1.6 p1.7 p2.0 p2.1 p2.2 p2.3 usb peripheral controller 1k byte ram full / low speed transceiver cip-51 8051 controller core 16k byte otp program memory 256 byte sram 1024 byte xram d+ d- vbus uart1 port 0 drivers port 1 drivers port 3 drivers port 2 drivers voltage regulator regulator core power peripheral power gnd regin vdd in-system programming hardware vpp system clock setup external oscillator internal oscillator low freq. oscillator clock recovery xtal1 xtal2 analog peripherals (c8051t321) 2 comparators + - 10-bit 500ksps adc a m u x temp sensor vref vdd vdd vref gnd cp0, cp0a voltage reference vref + - cp1, cp1a rev. 1.1 19 c8051t620/621/320/321/322/323 figure 1.4. typical bus-powered connections vregin vbus vdd d+ d- gnd rst/ c2ck esd protection usb connector a 1ko-5ko pull-up resistor can be connected to vio* for added noise immunity. 1ko- 5ko reset signal supply net usb add decoupling/bypass capacitors close to each voltage supply pin. 0.1f 4.7f 1f add esd protection diodes designed for use with usb, such as littlefuse sp0503baht or equivalent. 1.8v to vdd vio* vio can be connected directly to vdd. vio* port i/o gpio debug signals connections needed for optional debug interface keep the usb shield ground isolated from the device ground. c2ck c2d gnd unused port pins should be left floating, configured to push-pull output, and driven high. gnd c2d *note : vio only appears on certain package options. if vio is not present, the rst pullup can connect to vdd. c8051t620/621/320/321/322/323 20 rev. 1.1 2. ordering information table 2.1. product selection guide ordering part number mips (peak) eprom code memory (bytes) ram (bytes) calibrated internal 48 mhz oscillator internal 80 khz oscillator usb with 1k endpoint ram supply voltage regulator smbus/i 2 c enhanced spi uarts timers (16-bit) programmable counter array digital port i/os 10-bit 500ksps adc internal voltage reference temperature sensor analog comparator lead-free (rohs compliant) package c8051t620-gm 48 16k 1 1280yyyyyy2 4y24yyy2yqfn32 c8051t621-gm 48 16k 1 1280yyyyyy2 4y24???2yqfn32 c8051t320-gq 2 48 16k 1 1280yyyyyy2 4y25yyy2ylqfp32 c8051t321-gm 3 48 16k 1 1280yyyyyy2 4y21yyy2yqfn28 c8051t322-gq 2 48 16k 1 1280yyyyyy2 4y25???2ylqfp32 c8051t323-gm 3 48 16k 1 1280yyyyyy2 4y21???2yqfn28 notes: 1. 512 bytes reserved for factory use. 2. pin compatible with the c8051f320-gq. 3. pin compatible with the c8051f321-gm. 4. lead plating material is 100% matte tin (sn). rev. 1.1 21 c8051t620/621/320/321/322/323 3. pin definitions table 3.1. pin definitions for the c8051t620/621/320/321/322/323 name pin number type description ?t620/1 ?t320/2 ?t321/3 v dd 7 6 6 power supply voltage. gnd 3 3 3 ground. rst / c2ck 10 9 9 d i/o d i/o device reset. open-drain ou tput of internal por or v dd monitor. an external s ource can initiate a system reset by driving this pin low for at least 10 s. clock signal for the c2 debug interface. p3.0/ c2d 11 10 10 d i/o d i/o port 3.0. bi-directional data signal for the c2 debug interface. regin 8 7 7 5 v regulator input. this pin is the input to the on-chip voltage regulator. vbus 9 8 8 d in vbus sense input. this pin should be connected to the vbus signal of a usb network. a 5 v signal on this pin indicates a usb network connection. d+ 4 4 4 d i/o usb d+. d- 5 5 5 d i/o usb d?. v io 6 - - v i/o supply voltage input. the voltage at this pin must be less than or equal to the core supply voltage (v dd ). p0.0 2 2 2 d i/o or a in port 0.0. p0.1 1 1 1 d i/o or a in port 0.1. p0.2 xtal1 32 32 28 d i/o or a in a in port 0.2. external clock input. this pin is the external oscillator return for a crystal or reso nator. see oscillator section. c8051t620/621/320/321/322/323 22 rev. 1.1 p0.3/ xtal2 31 31 27 d i/o or a in a out d in a in port 0.3. external clock output. this pin is the excitation driver for an external crystal or resonator. external clock input. this pin is the external clock input in external cmos clock mode. external clock input. this pin is the external clock input in capacitor or rc osc illator configurations. see oscillator section for complete details. p0.4 30 30 26 d i/o or a in port 0.4. p0.5 29 29 25 d i/o or a in port 0.5. p0.6/ cnvstr 28 28 24 d i/o or a in d in port 0.6. adc0 external convert star t or ida0 update source input. p0.7/ vref 27 27 23 d i/o or a in a i/o port 0.7 adc voltage reference p1.0 26 26 22 d i/o or a in port 1.0. p1.1 25 25 21 d i/o or a in port 1.1. p1.2 24 24 20 d i/o or a in port 1.2. p1.3 23 23 19 d i/o or a in port 1.3. p1.4 22 22 18 d i/o or a in port 1.4. table 3.1. pin definitions for the c8051t620/621/320/321/322/323(continued) name pin number type description ?t620/1 ?t320/2 ?t321/3 rev. 1.1 23 c8051t620/621/320/321/322/323 p1.5/ v pp 21 21 17 d i/o or a in a in port 1.5. v pp programming supply voltage p1.6 20 20 16 d i/o or a in port 1.6. p1.7 19 19 15 d i/o or a in port 1.7. p2.0 18 18 14 d i/o or a in port 2.0. p2.1 17 17 13 d i/o or a in port 2.1. p2.2 16 16 12 d i/o or a in port 2.2. p2.3 15 15 11 d i/o or a in port 2.3. p2.4 14 14 - d i/o or a in port 2.4. p2.5 13 13 - d i/o or a in port 2.5. p2.6 12 12 - d i/o or a in port 2.6. p2.7 - 11 - d i/o or a in port 2.7. table 3.1. pin definitions for the c8051t620/621/320/321/322/323(continued) name pin number type description ?t620/1 ?t320/2 ?t321/3 c8051t620/621/320/321/322/323 24 rev. 1.1 figure 3.1. qfn-32 pinout diagram (top view) 17 25 p1.1 16 8 32 31 30 29 28 27 26 1 2 3 4 5 6 7 9 10 11 12 13 14 15 24 23 22 21 20 19 18 gnd (optional) c8051t620/1-gm top view p1.0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 gnd vdd d- vio p2.6 p2.5 p2.4 p2.3 p2.2 p2.0 p2.1 p1.7 p1.6 p1.5 / vpp p1.4 p1.3 p1.2 regin p3.0 / c2d d+ rst / c2ck vbus rev. 1.1 25 c8051t620/621/320/321/322/323 figure 3.2. lqfp-32 pinout diagram (top view) c8051t320/2-gq top view 1 p1.2 p1.7 p1.4 p1.3 p1.5 / vpp p2.0 p2.1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 p1.6 p3.0 / c2d p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p1.1 p1.0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 gnd regin d- vdd vbus d+ rst / c2ck c8051t620/621/320/321/322/323 26 rev. 1.1 figure 3.3. qfn-28 pinout diagram (top view) 28 27 26 25 24 23 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 21 20 19 18 17 16 15 gnd (optional) c8051t321/3-gm top view p1.0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 gnd p2.3 p2.2 p2.1 p2.0 p1.7 p1.6 p1.5 / vpp p1.4 p1.3 p1.2 p1.1 vdd d- regin d+ p3.0 / c2d rst / c2ck vbus rev. 1.1 27 c8051t620/621/320/321/322/323 4. lqfp-32 package specifications figure 4.1. lqfp-32 package drawing table 4.1. lqfp-32 package dimensions dimension min typ max dimension min typ max a??1.60 e 9.00 bsc. a1 0.05 ? 0.15 e1 7.00 bsc. a2 1.35 1.40 1.45 l 0.450.600.75 b 0.30 0.37 0.45 aaa 0.20 c 0.09 ? 0.20 bbb 0.20 d 9.00 bsc. ccc 0.10 d1 7.00 bsc. ddd 0.20 e 0.80 bsc. ? 0 3.5 7 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jede c outline ms-026, variation bba. 4. recommended card reflow profile is per the je dec/ipc j-std-020c specification for small body components. c8051t620/621/320/321/322/323 28 rev. 1.1 figure 4.2. lqfp-32 recommended pcb land pattern table 4.2. lqfp-32 pcb land pattern dimensions dimension min max dimension min max c1 8.40 8.50 x1 0.40 0.50 c2 8.40 8.50 y1 1.25 1.35 e0.80 notes: general 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design 4. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all pads. card assembly 7. a no-clean, type-3 solder paste is recommended. 8. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. rev. 1.1 29 c8051t620/621/320/321/322/323 5. qfn-32 package specifications figure 5.1. qfn-32 package drawing table 5.1. qfn-32 package dimensions dimension min typ max dimension min typ max a 0.80 0.90 1.00 e2 3.20 3.30 3.40 a1 0.00 0.02 0.05 l 0.30 0.40 0.50 b 0.18 0.25 0.30 l1 0.00 ? 0.15 d 5.00 bsc. aaa 0.15 d2 3.20 3.30 3.40 bbb 0.10 e 0.50 bsc. ddd 0.05 e 5.00 bsc. eee 0.08 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vhhd except for custom features d2, e2, and l which are toleranced per supplier designation. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components. c8051t620/621/320/321/322/323 30 rev. 1.1 figure 5.2. qfn-32 recommended pcb land pattern table 5.2. qfn-32 pcb land pattern dimensions dimension min max dimension min max c1 4.80 4.90 x2 3.20 3.40 c2 4.80 4.90 y1 0.75 0.85 e 0.50 bsc y2 3.20 3.40 x1 0.20 0.30 notes: general 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design 4. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 7. a 3x3 array of 1.0 mm openings on a 1.2 mm pitch should be used for the center pad to assure the proper paste volume. card assembly 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per the jedec/ipc j-std- 020c specification for small body components. rev. 1.1 31 c8051t620/621/320/321/322/323 6. qfn-28 package specifications figure 6.1. qfn-28 package drawing table 6.1. qfn-28 package dimensions dimension min typ max dimension min typ max a 0.80 0.90 1.00 l 0.35 0.55 0.65 a1 0.00 0.02 0.05 l1 0.00 ? 0.15 a3 0.25 ref aaa 0.15 b 0.18 0.23 0.30 bbb 0.10 d 5.00 bsc. ddd 0.05 d2 2.90 3.15 3.35 eee 0.08 e 0.50 bsc. z 0.44 e 5.00 bsc. y 0.18 e2 2.90 3.15 3.35 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vhhd except for custom features d2, e2, z, y, and l wh ich are toleranced per supplier designation. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components. c8051t620/621/320/321/322/323 32 rev. 1.1 figure 6.2. qfn-28 recommended pcb land pattern table 6.2. qfn-28 pcb land pattern dimensions dimension min max dimension min max c1 4.80 x2 3.20 3.30 c2 4.80 y1 0.85 0.95 e 0.50 y2 3.20 3.30 x1 0.20 0.30 notes: general 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. solder mask design 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design 5. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 8. a 3x3 array of 0.90mm openings on a 1.1 mm pitc h should be used for the center pad to assure the proper paste volume (67% paste coverage). card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per th e jedec/ipc j-std-020 specification for small body components. rev. 1.1 33 c8051t620/621/320/321/322/323 7. electrical characteristics 7.1. absolute m aximum specifications table 7.1. absolute maximum ratings parameter conditions min typ max units ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on rst or any port i/o pin (except v pp during program- ming) with respect to gnd v dd > 2.2 v v dd < 2.2 v ?0.3 ?0.3 ? ? 5.8 v dd + 3.6 v v voltage on v pp with respect to gnd during a programming oper- ation v dd > 2.4 v ?0.3 ? 7.0 v duration of high-voltage on v pp pin (cumulative) v pp > 3.6 v and in-applica- tion programming enabled or a non-zero value written to epctl 10 s voltage on v dd with respect to gnd regulator1 in normal mode regulator1 in bypass mode ?0.3 ?0.3 ? ? 4.2 1.98 v v maximum total current through v dd , v io , regin, or gnd ??500ma maximum output current sunk by rst or any port pin ??100ma note: stresses above those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation list ings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. c8051t620/621/320/321/322/323 34 rev. 1.1 7.2. electrical characteristics table 7.2. global electrical characteristics ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units supply voltage (note 1) regulator1 in normal mode regulator1 in bypass mode 1.8 1.75 3.0 ? 3.6 1.9 v v digital supply current with cpu active v dd = 1.8 v, clock = 48 mhz v dd = 1.8 v, clock = 1 mhz v dd = 3.3 v, clock = 48 mhz v dd = 3.3 v, clock = 1 mhz v dd = 3.6 v, clock = 48 mhz v dd = 3.6 v, clock = 1 mhz ? ? ? ? ? ? 9.4 1.6 11.0 1.7 11.1 1.8 11.4 ? 13.7 ? 13.8 ? ma ma ma ma ma ma digital supply current with cpu inactive (not accessing eprom) v dd = 1.8 v, clock = 48 mhz v dd = 1.8 v, clock = 1 mhz v dd = 3.3 v, clock = 48 mhz v dd = 3.3 v, clock = 1 mhz v dd = 3.6 v, clock = 48 mhz v dd = 3.6 v, clock = 1 mhz ? ? ? ? ? ? 4.6 0.4 5.1 0.45 5.1 0.5 5.5 ? 5.9 ? 6.0 ? ma ma ma ma ma ma digital supply current (shutdown) oscillator not running (stop mode), inter- nal regulator off ?.1? a oscillator not running (stop or suspend mode), internal regulator on ? 375 ? a digital supply current for usb module (usb active mode) v dd = 3.6 v, usb clock = 48 mhz v dd = 3.3 v, usb clock = 48 mhz ? ? 11.8 11.4 ? ? ma ma digital supply current for usb module (usb suspend mode) oscillator not running v dd monitor disabled ?60? a digital supply ram data reten- tion voltage ?1.5? v specified operating ? temperature range ?40 ? +85 c sysclk (system clock) (note 2) 0 ? 48 mhz tsysl (sysclk low time) 9.75 ? ? ns tsysh (sysclk high time) 9.75 ? ? ns notes: 1. analog performance is not guaranteed when v dd is below 1.8 v. 2. sysclk must be at least 32 khz to enable debugging. rev. 1.1 35 c8051t620/621/320/321/322/323 table 7.3. port i/o dc electrical characteristics v dd = 1.8 to 3.6 v, v io < v dd , ?40 to +85 c unless otherwise specified. parameters conditions min typ max units output high voltage i oh = ?10 a, port i/o push-pull i oh = ?3 ma, port i/o push-pull i oh = ?10 ma, port i/o push-pull v io ? 0.1 v io ? 0.2 ? ? ? v io ? 0.4 ? ? ? v output low voltage i ol = 10 a i ol = 8.5 ma i ol = 25 ma ? ? ? ? ? 0.6 0.1 0.4 ? v input high voltage 0.7 x v io ??v input low voltage ? ? 0.6 v input leakage ? current weak pullup off weak pullup on, v in = 0 v ?1 ? ? 25 +1 50 a a table 7.4. reset electrical characteristics ?40 to +85 c unless otherwise specified. parameter conditions min typ max units rst output low voltage i ol = 8.5 ma, ? v dd = 1.8 v to 3.6 v ??0.6v rst input high voltage 0.75 x v io ?? v rst input low voltage ? ? 0.6 v rst input pullup current rst = 0.0 v ? 25 50 a v dd por threshold (v rst ) 1.7 1.75 1.8 v missing clock detector time- out time from last system clock rising edge to reset initiation 500 625 750 s reset time delay delay between release of any reset source and code ? execution at location 0x0000 ??60s minimum rst low time to generate a system reset 15 ? ? s v dd monitor turn-on time v dd = v rst ? 0.1 v ? 50 ? s v dd monitor supply current ? 20 30 a c8051t620/621/320/321/322/323 36 rev. 1.1 table 7.5. internal voltage regulator electrical characteristics ?40 to +85 c unless otherwise specified. parameter conditions min typ max units voltage regulator (reg0) input voltage range 1, 3 2.7 ? 5.25 v output voltage (v dd ) 2 output current = 1 to 100 ma 3.3 3.45 3.6 v output current 2 ??100ma vbus detection input threshold 2.5 ? ? v bias current normal mode (reg0md = 0) low power mode (reg0md = 1) ? ? 83 38 98 52 a dropout voltage (v do ) 3 i dd = 1 ma i dd = 100 ma ? ? 1 100 ? ? mv/ma mv/ma voltage regulator (reg1) input voltage range 1.8 ? 3.6 v bias current normal mode (reg1md = 0) low power mode (reg1md = 1) ? ? 320 425 175 a a notes: 1. input range specified for regulation. when an exte rnal regulator is used, should be tied to v dd . 2. output current is total regulator out put, including any current required by the c8051t620/621/320/321/322/323. 3. the minimum input voltage is 2.7 v or v dd + v do (max load), whichever is greater. table 7.6. eprom electrical characteristics parameter conditions min typ max units eprom size (note 1) c8051t620/621/320/321/322/ 323 16384 ? ? bytes write cycle time (per byte) (note 2) 105 155 205 s in-application programming write cycle time (per byte) (note 3) capacitor on v pp = 4.7 f and fully discharged capacitor on v pp = 4.7 f and initially charged to 3.3 v ? ? 37 26 ? ? ms ms programming voltage (v pp ) 5.75 6.0 6.25 v capacitor on v pp for in-appli- cation programming ?4.7? f notes: 1. 512 bytes at location 0x3e00 to 0x3fff are not available for program storage 2. for devices with a date code prior to 1040, the programmi ng time over the c2 interf ace is twice as long. see section 18.1.1 for more information. 3. duration of write time is largely dependent on vio vo ltage, supply voltage, and residual charge on the vpp capacitor. the majority of the wr ite time consists of charging the voltage on vpp to 6.0 v. these measurements include the vpp ramp time and vdd = vio = 3.3 v rev. 1.1 37 c8051t620/621/320/321/322/323 table 7.7. internal high-frequency oscillator electrical characteristics v dd = 2.7 to 3.6 v; t a = ?40 to +85 c unless otherwise specif ied; using factory-calibrated settings. parameter conditions min typ max units oscillator frequency ifcn = 11b 47.28 48 48.72 mhz oscillator supply current ? (from v dd ) 25 c, v dd = 3.0 v, oscicn.7 = 1, oscicn.5 = 0 ? 900 1000 a power supply sensitivity constant temperature ? 0.02 ? %/v temperature sensitivity constant supply ? 20 ? ppm/c note: represents mean 1 standard deviation. table 7.8. internal low-frequency oscillator electrical characteristics v dd = 2.7 to 3.6 v; t a = ?40 to +85 c unless otherwise specif ied; using factory-calibrated settings. parameter conditions min typ max units oscillator frequency oscld = 11b 72 80 88 khz oscillator supply current ? (from v dd ) 25 c, v dd = 3.0 v, osclcn.7 = 1 ?36a power supply sensitivity con stant temperature ? 0.09 ? %/v temperature sensitivity constant supply ? 30 ? ppm/c note: represents mean 1 standard deviation. table 7.9. external oscillator electrical characteristics v dd = 2.7 to 3.6 v; t a = ?40 to +85 c unless otherwise specified. parameter conditions min typ max units external crystal frequency .02 ? 30 mhz external cmos oscillator fre- quency 0?48mhz c8051t620/621/320/321/322/323 38 rev. 1.1 table 7.10. adc0 electrical characteristics v dd = 3.0 v, vref = 2.40 v (refsl=0), pga gain = 1, ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity ? 0.5 1 lsb differential nonlinearity guaranteed monotonic ? 0.5 1 lsb offset error ?2 0 +2 lsb full scale error ?2 0 +2 lsb offset temperature coefficient ? 45 ? ppm/c dynamic performance (10 khz sine-wave single-en ded input, 1 db below full scale, 500 ksps) signal-to-noise plus distortion 56 60 ? db total harmonic distortion up to the 5th harmonic ? 70 ? db spurious-free dynamic range ? 93 ? db conversion rate sar conversion clock ? ? 8.00 mhz conversion time in sar clocks 10-bit mode 8-bit mode 13 11 ? ? ? ? clocks clocks track/hold acquisition time vdd > 2.0 v vdd < 2.0 v 300 2.0 ? ? ? ? ns s throughput rate ? ? 500 ksps analog inputs adc input voltage range single ended (ain+ ? gnd) 0 ? vref v absolute pin voltage with respect to gnd 0?v io v sampling capacitance gain = 1x (amp0gn0 = 1) gain = 0.5x (amp0gn0 = 0) ? ? 5 3 ? ? pf pf input multiplexer impedance ? 5 ? k ? power specifications power supply current ? (v dd supplied to adc0) operating mode, 500 ksps ? 600 900 a power supply rejection ? ?70 ? db note: represents one standard deviation from the mean. rev. 1.1 39 c8051t620/621/320/321/322/323 table 7.11. temperature sensor electrical characteristics v dd = 3.0 v, ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units linearity ? 0.2 ? c slope ? 2.87 ? mv/c slope error* ? 337 ? v/c offset temp = 0 c ? 912 ? mv offset error* temp = 0 c ? 11 ? mv note: represents one standard deviation from the mean. table 7.12. voltage reference electrical characteristics v dd = 3.0 v; ?40 to +85 c unless otherwise specified. parameter conditions min typ max units internal reference (refbe = 1) output voltage 1.2 v setting, 25 c ambient 2.4 v setting, 25 c ambient 1.1 2.3 1.2 2.4 1.3 2.5 v vref short-circuit current ? 4.5 6 ma vref temperature ? coefficient ? 15 ? ppm/c load regulation load = 0 to 200 a to gnd, 1.2 v setting load = 0 to 200 a to gnd, 2.4 v setting ? ? 3.3 5.7 ? ? v/a v/a vref turn-on time (1.2 v setting) 4.7 f tantalum, 0.1 f ceramic bypass ? 1.2 ? ms 0.1 f ceramic bypass ? 25 ? s vref turn-on time (2.4 v setting) 4.7 f tantalum, 0.1 f ceramic bypass ? 3.8 ? ms 0.1 f ceramic bypass ? 90 ? s power supply rejection 1 .2 v setting ? 160 ? v/v 2.4 v setting ? 330 ? v/v external reference (refbe = 0) input voltage range 0 ? v dd v input current sample rate = 500 ksps; vref = 3.0 v ? 12 ? a power specifications reference bias generator refbe = 1 or tempe = 1 ? 75 100 a c8051t620/621/320/321/322/323 40 rev. 1.1 table 7.13. comparator electrical characteristics v dd = 3.0 v, ?40 to +85 c unless otherwise noted. parameter conditions min typ max units response time: mode 0, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 240 ? ns cp0+ ? cp0? = ?100 mv ? 240 ? ns response time: mode 1, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 400 ? ns cp0+ ? cp0? = ?100 mv ? 400 ? ns response time: mode 2, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 650 ? ns cp0+ ? cp0? = ?100 mv ? 1100 ? ns response time: mode 3, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 2000 ? ns cp0+ ? cp0? = ?100 mv ? 5500 ? ns common-mode rejection ratio ? 1.0 4 mv/v positive hysteresis 1 cp0hyp1?0 = 00 ? 0 1 mv positive hysteresis 2 cp0hyp1?0 = 01 2 5 8 mv positive hysteresis 3 cp0hyp1?0 = 10 6 10 14 mv positive hysteresis 4 cp0hyp1?0 = 11 12 20 28 mv negative hysteresis 1 cp0hyn1?0 = 00 0 1 mv negative hysteresis 2 cp0hyn1?0 = 01 2 5 8 mv negative hysteresis 3 cp0hyn1?0 = 10 6 10 14 mv negative hysteresis 4 cp0hyn1?0 = 11 12 20 28 mv inverting or non- inverting input voltage range ?0.25 ? v dd + 0.25 v input capacitance ? 4 ? pf input offset voltage ?7.5 ? +7.5 mv power supply power supply rejection ? 0.5 ? mv/v power-up time ? 10 ? s supply current at dc mode 0 ? 26 50 a mode 1 ? 10 20 a mode 2 ? 3 6 a mode 3 ? 0.5 2 a note: vcm is the common-mode voltage on cp0+ and cp0?. rev. 1.1 41 c8051t620/621/320/321/322/323 table 7.14. usb transceiver electrical characteristics v dd = 3.0 v to 3.6 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units transmitter output high voltage (v oh )2 . 8 ? ? v output low voltage (v ol )? ? 0 . 8 v output crossover point (v crs ) 1.3 ? 2.0 v output impedance (z drv ) driving high driving low ? ? 36 36 ? ? ? pull-up resistance (r pu ) full speed (d+ pull-up) low speed (d- pull-up) 1.425 1.5 1.575 k ? output rise time (t r ) low speed full speed 75 4 ? ? 300 20 ns output fall time (t f ) low speed full speed 75 4 ? ? 300 20 ns receiver differential input sensitivity (v di ) | (d+) - (d-) | 0.2 ? ? v differential input common mode range (v cm ) 0.8 ? 2.5 v input leakage current (i l ) pullups disabled ? <1.0 ? a note: refer to the usb specification for timing diagrams and symbol definitions. c8051t620/621/320/321/322/323 42 rev. 1.1 7.3. typical performance curves figure 7.1. normal mode digital supply current vs. frequency (mpce = 1) figure 7.2. idle mode digital supply current vs. frequency (mpce = 1) 0.0 2.0 4.0 6.0 8.0 10.0 12.0 0 5 10 15 20 25 30 35 40 45 50 idd (ma) sysclk (mhz) v dd = 1.8 v v dd = 3.3 v 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0 5 10 15 20 25 30 35 40 45 50 idd (ma) sysclk (mhz) v dd = 3.3 v v dd = 1.8 v rev. 1.1 43 c8051t620/621/320/321/322/323 8. 10-bit adc (adc0, c8051t620/320/321 only) adc0 on the c8051t620/320/321 is a 500 ksps, 10 -bit successive-approximation-register (sar) adc with integrated track-and-hold, a gain stage programmable to 1x or 0.5x, and a programmable window detector. the adc is fully configur able under software control via special function registers. the adc may be configured to measure various different signal s using the analog multiple xer described in section ?8.5. adc0 analog multiplexer (c8051t620/320/321 only)? on page 53. the voltage reference for the adc is selected as described in section ?10. voltage re ference options? on page 57. the adc0 subsystem is enabled only when the ad0en bit in the adc0 control register (adc0cn) is set to logic 1. the adc0 sub- system is in low power shutdown when this bit is logic 0. figure 8.1. adc0 functional block diagram adc0cf amp0gn0 ad08be ad0ljst ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 10-bit sar adc ref sysclk adc0h 32 adc0cn ad0cm0 ad0cm1 ad0cm2 ad0wint ad0busy ad0int ad0tm ad0en timer 0 overflow timer 2 overflow timer 1 overflow start conversion 000 ad0busy (w) vdd adc0lth ad0wint 001 010 011 100 cnvstr input window compare logic 101 timer 3 overflow adc0ltl adc0gth adc0gtl adc0l ain from amux0 x1 or x0.5 amp0gn0 c8051t620/621/320/321/322/323 44 rev. 1.1 8.1. output code formatting the adc measures the input voltage with reference to gnd. the registers adc0h and adc0l contain the high and low bytes of the output conversion code from the adc at the completion of each conversion. data can be right-justified or left-justified, depending on the setting of the ad0ljst bit. conversion codes are represented as 10-bit unsigned integers. inputs ar e measured from 0 to vref x 1023/1024. example codes are shown below for both right-justified and left -justified data. unused bits in the adc0h and adc0l registers are set to 0. 8.2. 8-bit mode setting the adc08be bit in register adc0cf to 1 will put the adc in 8-bit mode. in 8-bit mode, only the 8 msbs of data are converted, and the adc0h register holds the results. the ad0ljst bit is ignored for 8- bit mode. 8-bit conversions take two fewer sar clock cycles than 10-bit co nversions, so the conversion is completed faster, and a 500 ksps sampling rate can be achieved with a slower sar clock. 8.3. modes of operation adc0 has a maximum conversion speed of 500 ksps. t he adc0 conversion clock is a divided version of the system clock, determined by the ad0sc bits in the adc0cf register. 8.3.1. starting a conversion a conversion can be initiated in one of six ways, depending on the programmed states of the adc0 start of conversion mode bits (ad0cm2 ? 0) in register adc0cn. conversions may be initiated by one of the fol- lowing: 1. writing a 1 to the ad0busy bit of register adc0cn 2. a timer 0 overflow (i.e., ti med continuous conversions) 3. a timer 2 overflow 4. a timer 1 overflow 5. a rising edge on the cnvstr input signal 6. a timer 3 overflow writing a 1 to ad0busy provides software contro l of adc0 whereby conversions are performed "on- demand". during conversion, the ad0busy bit is set to logic 1 and reset to logic 0 when the conversion is complete. the falling edge of ad0bu sy triggers an interrupt (when enabl ed) and sets the adc0 interrupt flag (ad0int). note: when polling for adc conversion completions, the adc0 in terrupt flag (ad0int) should be used. converted data is available in th e adc0 data registers, adc0h:adc0l, when bit ad0int is logic 1. note that when timer 2 or timer 3 overfl ows are used as the conversi on source, low byte over- flows are used if timer 2/3 is in 8-bit mode; high by te overflows are used if timer 2/3 is in 16-bit mode. see section ?28. timers? on page 240 for timer configuration. important note about using cnvstr: the cnvstr input pin also functions as a port i/o pin. when the cnvstr input is used as t he adc0 conversion source, the associated pin should be skipped by the digi- tal crossbar. see section ?22. port input/output? on page 133 for details on port i/o configuration. input voltage right-justified adc0h:adc0l (ad0ljst = 0) left-justified adc0h:adc0l (ad0ljst = 1) vref x 1023/1024 0x03ff 0xffc0 vref x 512/1024 0x0200 0x8000 vref x 256/1024 0x0100 0x4000 0 0x0000 0x0000 rev. 1.1 45 c8051t620/621/320/321/322/323 8.3.2. tracking modes the ad0tm bit in regi ster adc0cn enables "delayed conversion s", and will delay the actual conversion start by three sar clock cycles, during which time t he adc will continue to track th e input. if ad0tm is left at logic 0, a conversion will begin im mediately, without the extra tracking time. for internal start-of-conver- sion sources, the adc will track anyt ime it is not pe rforming a conver sion. when the cnvstr signal is used to initiate conversions, adc0 will track either when ad0tm is logic 1, or when ad0tm is logic 0 and cnvstr is held low. see figure 8.2 for track and convert timing details. delayed conversion mode is use- ful when amux settings are frequently changed, due to the settling time requirements described in section ?8.3.3. settling time requirements? on page 46. figure 8.2. 10-bit adc track and conversion example timing write '1' to ad0busy, timer 0, timer 2, timer 1 overflow (ad0cm[2:0]=000, 001, 010, 011) ad0tm=1 track convert track ad0tm=0 track convert track sar clocks sar clocks b. adc timing for internal trigger source cnvstr (ad0cm[2:0]=1xx) ad0tm=1 a. adc timing for ex ternal trigger source track convert n/c ad0tm=0 track convert track *conversion ends at rising edge of 12 th clock in 8-bit mode *conversion ends at rising edge of 15 th clock in 8-bit mode *conversion ends at rising edge of 12 th clock in 8-bit mode 123456789 10 11 12* 13 14 123456789 10 11 12 13 14 15* 16 17 n/c sar clocks *conversion ends at rising edge of 15 th clock in 8-bit mode sar clocks 123456789 10 11 12 13 14 15* 16 17 123456789 10 11 12* 13 14 c8051t620/621/320/321/322/323 46 rev. 1.1 8.3.3. settling time requirements a minimum tracking time is required before each conversi on to ensure that an accurate conversion is per- formed. this tracking time is determined by any se ries impedance, including the amux0 resistance, the the adc0 sampling capacitance, and the accuracy requir ed for the conversion. note that in delayed track- ing mode, three sar clocks are used for tracking at th e start of every conversion. for many applications, these three sar clocks will meet the mi nimum tracking ti me requirements. figure 8.3 shows the equivalent adc0 input circuit. the required adc0 settling time for a given settling accuracy (sa) may be approximated by equation 8. 1. see table 7.10 for adc0 minimum settling time requirements as well as the mux impedance and sampling capacitor values. equation 8.1. adc0 settling time requirements where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the r equired settling time in seconds r total is the sum of the amux0 resistance and any external source resistance. n is the ad c resolution in bits (10). figure 8.3. adc0 equivalent input circuits t 2 n sa ------ - ?? ?? r total c sample ? r mux c sample rc input = r mux * c sample mux select input pin note: see electrical specification tables for r mux and c sample parameters. rev. 1.1 47 c8051t620/621/320/321/322/323 sfr address = 0xbc sfr definition 8.1. adc0 cf: adc0 configuration bit76543210 name ad0sc[4:0] ad0ljst ad08be amp0gn0 type r/w r/w r/w r/w reset 11111001 bit name function 7:3 ad0sc[4:0] adc0 sar conversion cl ock period bits. sar conversion clock is derived from syste m clock by the following equation, where ad0sc refers to the 5-bit value held in bits ad0sc4 ? 0. sar conversion clock requirements are given in the adc specification table. note: if the memory power controller is enabled (mpce = '1'), ad0sc must be set to at least "00001" for proper adc operation. 2ad0ljst adc0 left justify select. 0: data in adc0h:adc0l re gisters are right-justified. 1: data in adc0h:adc0l re gisters are left-justified. note: the ad0ljst bit is only valid for 10-bit mode (ad08be = 0). 1ad08be 8-bit mode enable. 0: adc operates in 10-bit mode (normal). 1: adc operates in 8-bit mode. note: when ad08be is set to 1, the ad0ljst bit is ignored. 0amp0gn0 adc gain control bit. 0: gain = 0.5 1: gain = 1 ad0sc sysclk clk sar ------------ ---------- - 1? = c8051t620/621/320/321/322/323 48 rev. 1.1 sfr address = 0xbe sfr address = 0xbd sfr definition 8.2. adc0h: adc0 data word msb bit76543210 name adc0h[7:0] type r/w reset 00000000 bit name function 7:0 adc0h[7:0] adc0 data word high-order bits. for ad0ljst = 0: bits 7 ? 2 will read 000000b. bits 1 ? 0 are the upper 2 bits of the 10- bit adc0 data word. for ad0ljst = 1: bits 7 ? 0 are the most-significant bits of the 10-bit adc0 data word. note: in 8-bit mode ad0ljst is ignored, and adc0h holds the 8-bit data word. sfr definition 8.3. adc0l: adc0 data word lsb bit76543210 name adc0l[7:0] type r/w reset 00000000 bit name function 7:0 adc0l[7:0] adc0 data word low-order bits. for ad0ljst = 0: bits 7 ? 0 are the lower 8 bits of the 10-bit data word. for ad0ljst = 1: bits 7 ? 6 are the lower 2 bits of the 10-bit data word. bits 5 ? 0 will read 000000b. note: in 8-bit mode ad0ljst is ignored, and adc0l will read back 00000000b. rev. 1.1 49 c8051t620/621/320/321/322/323 sfr address = 0xe8; bit-addressable sfr definition 8.4. a dc0cn: adc0 control bit76543210 name ad0en ad0tm ad0int ad0busy ad0wint ad0cm[2:0] type r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7ad0en adc0 enable bit. 0: adc0 disabled. adc0 is in low-power shutdown. 1: adc0 enabled. adc0 is active and ready for data conversions. 6ad0tm adc0 track mode bit. 0: normal track mode: when adc0 is ena bled, tracking is continuous unless a con- version is in progress. conversion begins immediately on start-of-conversion event, as defined by ad0cm[2:0]. 1: delayed track mode: when adc0 is enabled, input is tracked when a conversion is not in progress. a start-of-conversion sign al initiates three sar clocks of additional tracking, and then begins the conversion. 5ad0int adc0 conversion comple te interrupt flag. 0: adc0 has not completed a data conv ersion since ad0int was last cleared. 1: adc0 has completed a data conversion. 4ad0busy adc0 busy bit. read: 0: adc0 conversion is not in progress. 1: adc0 conversion is in prog- ress. write: 0: no effect. 1: initiates adc0 conversion if ad0cm[2 : 0] = 000b 3 ad0wint adc0 window compare interrupt flag. 0: adc0 window comparison data match ha s not occurred since this flag was last cleared. 1: adc0 window comparison data match has occurred. 2:0 ad0cm[2:0] adc0 start of conversion mode select. 000: adc0 start-of-conversion s ource is write of 1 to ad0busy. 001: adc0 start-of-conversion source is overflow of timer 0. 010: adc0 start-of-conversion source is overflow of timer 2. 011: adc0 start-of-conversion source is overflow of timer 1. 100: adc0 start-of-conversion source is rising edge of external cnvstr. 101: adc0 start-of-conversion source is overflow of timer 3. 11x: reserved. c8051t620/621/320/321/322/323 50 rev. 1.1 8.4. programmable window detector the adc programmable window detector continuously compares the adc0 output registers to user-pro- grammed limits, and notifies the system when a desired co ndition is detected. this is especially effective in an interrupt-driven system, saving code space and cpu ba ndwidth while delivering faster system response times. the window detector interrupt flag (ad0wint in register adc0cn) can also be used in polled mode. the adc0 greater-than (adc0gth, adc0gtl) and less-than (adc0lth, adc0ltl) registers hold the comparison valu es. the window detector flag can be programmed to indicate when mea- sured data is inside or outside of the user-programmed limits, depending on the contents of the adc0 less-than and adc0 greater-than registers. sfr address = 0xc4 sfr address = 0xc3 sfr definition 8.5. adc0gth: adc0 greater-than data high byte bit76543210 name adc0gth[7:0] type r/w reset 11111111 bit name function 7:0 adc0gth[7:0] adc0 greater-than data word high-order bits. sfr definition 8.6. adc0gtl: adc0 greater-than data low byte bit76543210 name adc0gtl[7:0] type r/w reset 11111111 bit name function 7:0 adc0gtl[7:0] adc0 greater-than data word low-order bits. rev. 1.1 51 c8051t620/621/320/321/322/323 sfr address = 0xc6 sfr address = 0xc5 sfr definition 8.7. adc0lth: adc0 less-than data high byte bit76543210 name adc0lth[7:0] type r/w reset 00000000 bit name function 7:0 adc0lth[7:0] adc0 less-than data word high-order bits. sfr definition 8.8. adc0ltl: adc0 less -than data low byte bit76543210 name adc0ltl[7:0] type r/w reset 00000000 bit name function 7:0 adc0ltl[7:0] adc0 less-than data word low-order bits. c8051t620/621/320/321/322/323 52 rev. 1.1 8.4.1. window detector example figure 8.4 shows two example window comparisons for right-justified data, with adc0lth:adc0ltl = 0x0080 (128d) and adc0gth: adc0gtl = 0x0040 (64d). the input voltage can range from 0 to vref x (1023/1024) with respect to gnd, and is represented by a 10-bit unsigned integer value. in the left example, an ad0wint interrup t will be generated if the adc0 conversion word (adc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0x0040 < adc0h:adc0l < 0x0080). in the right example, and ad0wint interrup t will be generated if the adc0 conversion word is outside of the range defined by the adc0gt and adc0lt registers (if adc0h:adc0l < 0x0040 or adc0h:adc0l > 0x0080) . figure 8.5 shows an example using left-justi- fied data with the same comparison values. figure 8.4. adc window compare example: right-justified data figure 8.5. adc window compare example: left-justified data 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl adc0gth:adc0gtl rev. 1.1 53 c8051t620/621/320/321/322/323 8.5. adc0 analog mu ltiplexer (c8051t620/320/321 only) adc0 on the c8051t620/320/321 uses an analog input mult iplexer to select the posi tive input to the adc. any of the following may be selected as the positive input: port 1, 2, p3.0 and some port 0 i/o pins, the on- chip temperature sensor, or the positive power supply (v dd ). the adc0 input channel is selected in the amx0p register described in sfr definition 8.9. figure 8.6. adc0 multiplexer block diagram important note about adc0 input configuration: port pins selected as adc0 inputs should be config- ured as analog inputs, and should be skipped by the digital crossbar. to configure a port pin for analog input, set to 0 the corresponding bit in register pnmdin. to force the crossbar to skip a port pin, set to 1 the corresponding bit in register pnskip. see section ?22. port input/output? on page 133 for more port i/o configuration details. adc0 temp sensor amux vdd amx0p amx0p4 amx0p3 amx0p2 amx0p1 amx0p0 p1.0 p0.5 p0.0 p0.4 p0.1 p3.0 c8051t620/621/320/321/322/323 54 rev. 1.1 sfr address = 0xbb sfr definition 8.9. amx0p: amux0 positive channel select bit76543210 name amx0p[4:0] type rrr r/w reset 10000000 bit name function 7:5 unused unused. read = 10 0b; write = don?t care. 4:0 amx0p[4:0] amux0 positive input selection. 00000: p1.0 00001: p1.1 00010: p1.2 00011: p1.3 00100: p1.4 00101: p1.5 00110: p1.6 00111: p1.7 01000: p2.0 01001: p2.1 01010: p2.2 01011: p2.3 01100: p2.4(c8051t320/2 and c8051t620/1 only) 01101: p2.5(c8051t320/2 and c8051t620/1 only) 01110: p2.6 (c8051t320/2 and c8051t620/1 only) 01111: p2.7 (c8051t320/2 only) 10000: p3.0 10001: p0.0 10010: p0.1 10011: p0.4 10100: p0.5 10101-11101: reserved 11110: temp sensor 11111: v dd rev. 1.1 55 c8051t620/621/320/321/322/323 9. temperature sensor (c8051t620/320/321 only) an on-chip temperature sensor is included on the c8051t620/320/321 which can be directly accessed via the adc multiplexer in single-ended configuration. to use the adc to measure the temperature sensor, the adc mux channel should be configured to connect to the temperature sensor . the temperature sensor transfer function is shown in fi gure 9.1. the output voltage (v temp ) is the positive adc input when the adc multiplexer is set corr ectly. the tempe bit in register ref0 cn enables/disables the temperature sensor, as described in sfr definition 10.1. while di sabled, the temperature sensor defaults to a high impedance state and any adc measur ements performed on th e sensor will result in meaningless data. refer to table 7.11 for the slope and offs et parameters of the temperature sensor. figure 9.1. temperature sensor transfer function temperature voltage v temp = ( slope x temp c ) + offset offset (v at 0 celsius) slope (v / deg c) temp c = (v temp - offset ) / slope c8051t620/621/320/321/322/323 56 rev. 1.1 9.1. calibration the uncalibrated temperature sensor output is extrem ely linear and suitable for relative temperature mea- surements (see table 7.11 on page 39 for specifications). for absolute temperature measurements, offset and/or gain calibration is recommended. a single-point offset measurement of the temper ature sensor is performed on each device during produc- tion test. the toffh and toffl calibration values represent the output of the adc when reading the temperature sensor at 0 degrees celsius, and using the internal regulator as a voltage reference. the toffh and toffl values can be read from eprom memory and are located at 0x3ffb (toffh) and 0x3ffa (toffl). the temperature sensor offset info rmation is left-justified, so toffh contains the 8 most-significant bits of the calibration value and toff l.7-6 contain the 2 least-significant bits of the cali- bration value, as shown in figure 9.2. one lsb of this measurement is equivalent to one lsb of the adc output under the measurement conditions. figure 9.2. toffh and toffl calibration value orientation figure 9.3 shows the typical temperature sensor error assuming a 1-point calibration at 0 c. parameters that affect adc measurement, in particular the voltage reference value, will also affect temperature measurement. figure 9.3. temperature sensor error with 1-point calibration at 0 celsius toffh toffl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b it 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10-bit temperature sensor offset calibration value -40.00 -20.00 0.00 20.00 40.00 60.00 80.00 temperature (degrees c) error (degrees c) -5.00 -4.00 -3.00 -2.00 -1.00 0.00 1.00 2.00 3.00 4.00 5.00 -5.00 -4.00 -3.00 -2.00 -1.00 0.00 1.00 2.00 3.00 4.00 5.00 rev. 1.1 57 c8051t620/621/320/321/322/323 10. voltage reference options the voltage reference multiplexer for the adc is configurable to use an externally connected voltage refer- ence, the on-chip reference voltage generator routed to the vref pin, the unregulated power supply volt- age (v dd ), or the regulated 1.8 v internal supply (see figure 10.1). the refsl bit in the reference control register (ref0 cn, sfr definition 10.1) selects the reference source for the adc. for an external source or the on-chip reference, refsl should be set to 0 to select the vref pin. to use v dd as the ref- erence source, refsl should be set to 1. to override this selection and use the internal regulator as the reference source, the rego vr bit can be set to 1. the biase bit enables the inte rnal voltage bias ge nerator, which is used by ma ny of the analo g peripherals on the device. this bias is automatically enabled when any peripheral which requires it is enabled, and it does not need to be enabled manually. the bias generator may be enabled manually by writing a 1 to the biase bit in register ref0cn. the el ectrical specifications for the volt age reference circuit are given in table 7.12. the c8051t620/320/321 devices also include an on-ch ip voltage reference circuit which consists of a 1.2 v, temperature stable bandgap voltage reference generator and a selectable-gain output buffer ampli- fier. the buffer is configured for 1x or 2x gain usi ng the refbgs bit in register ref0cn. on the 1x gain setting the output voltage is nominally 1.2 v, and on th e 2x gain setting the output voltage is nominally 2.4 v. the on-chip voltage reference can be driven on the vref pin by setting the refbe bit in register ref0cn to a 1. the maximum load seen by the vref pin must be less than 200 a to gnd. bypass capacitors of 0.1 f and 4.7 f are recommended from the vref pin to gnd, an d a minimum of 0.1uf is required. if the on-chip reference is not used, the refbe bit should be cleared to 0. electrical specifica- tions for the on-chip voltage reference are given in table 7.12. important note about the vref pin: when using either an external vo ltage reference or the on-chip ref- erence circuitry, the vref pin should be configured as an analog pin and skipped by the digital crossbar. refer to section ?22. port input/output? on page 133 for the location of the vref pin, as well as details of how to configure the pin in analog mode and to be skipped by the crossbar. figure 10.1. voltage reference functional block diagram to analog mux vdd vref r1 vdd external voltage reference circuit gnd temp sensor en bias generator to adc, idac, internal oscillators, reference, tempsensor en ioscen 0 1 ref0cn refsl tempe biase refbe regovr refbgs refbe recommended bypass capacitors + 4.7? f0.1 ? f vref (to adc) 0 1 internal regulator regovr 1.2v reference en 1x/2x refbgs c8051t620/621/320/321/322/323 58 rev. 1.1 sfr address = 0xd1 sfr definition 10.1. ref0 cn: reference control bit76543210 name refbgs regovr refsl tempe biase refbe type r/w r r r/w r/w r/w r/w r/w reset 00000000 bit name function 7 refbgs reference buffer gain select. this bit selects between 1x and 2x gain for the on-chip voltage reference buffer. 0: 2x gain 1: 1x gain 6:5 unused unused. read = 00b; write = don?t care. 4regovr regulator reference override. this bit ?overrides? the refsl bit, and allows the internal regulator to be used as a ref- erence source. 0: the voltage reference source is selected by the refsl bit. 1: the internal regulator is used as the voltage reference. 3 refsl voltage reference select. this bit selects the adcs voltage reference. 0: v ref pin used as voltage reference. 1: v dd used as voltage reference. 2 tempe temperature sensor enable bit. 0: internal temperature sensor off. 1: internal temperature sensor on. 1 biase internal analog bias generator enable bit. 0: internal bias generator off. 1: internal bias generator on. 0 refbe on-chip reference buffer enable bit. 0: on-chip reference buffer off. 1: on-chip reference buffer on. internal voltage reference driven on the v ref pin. rev. 1.1 59 c8051t620/621/320/321/322/323 11. voltage regulators (reg0 and reg1) c8051t620/621/320/321/322/323 device s include two internal voltage regulators: one regulates a voltage source on regin to 3.45 v (reg0), and the other regulates the internal core supply to 1.8 v from a v dd supply of 1.8 to 3.6 v (reg1). when ena bled, the reg0 output appears on the v dd pin and can be used to power external devices. reg0 can be enabled/dis abled by software using bit reg0dis in register reg01cn (sfr definition 11.1). reg1 has two powe r-saving modes built into the regulator to help reduce current consumption in low-power applications. these modes are accessed through the reg01cn register. electrical characteristics for the on-chi p regulators are specified in table 7.5 on page 36. note that the vbus signal must be connected to th e vbus pin when using the device in a usb network. the vbus signal should only be connected to the re gin pin when operating the device as a bus-powered function. reg0 configuration options are shown in figure 11.1?figure 11.4. 11.1. voltage regulator (reg0) 11.1.1. regulator mode selection reg0 offers a low power mode intended for use when the device is in suspend mode. in this low power mode, the reg0 output remains as specified; however the reg0 dynami c performance (response time) is degraded. see table 7.5 for normal and low power mo de supply current specifications. the reg0 mode selection is controlled via the re g0md bit in register reg01cn. 11.1.2. vbus detection when the usb function controller is used (see se ction section ?23. univer sal serial bus controller (usb0)? on page 155), the vbus si gnal should be co nnected to the vbus pin. the vbstat bit (register reg01cn) indicates the current logic level of the vbu s signal. if enabled, a vbus interrupt will be gener- ated when the vbus signal has eith er a falling or rising edge. the vbu s interrupt is edg e-sensitive, and has no associated interrupt pending flag. see table 7.5 for vbus input parameters. important note: when usb is selected as a re set source, a system reset w ill be generated when a falling or rising edge occurs on the vbus pin. see section ?2 0. reset sources? on page 116 for details on select- ing usb as a reset source. figure 11.1. reg0 configuration: usb bus-powered voltage regulator (reg0) 5v in 3v out vbus sense regin vbus from vbus to 3 v power net device power net vdd c8051t620/621/320/321/322/323 60 rev. 1.1 figure 11.2. reg0 configuration: usb self-powered figure 11.3. reg0 configuration: usb self-powered, regulator disabled voltage regulator (reg0) 5 v in 3 v out vbus sense regin vbus to 3 v power net device power net vdd from 5 v power net from vbus voltage regulator (reg0) 5 v in 3 v out vbus sense regin vbus from 3 v power net device power net vdd from vbus rev. 1.1 61 c8051t620/621/320/321/322/323 figure 11.4. reg0 configuration: no usb connection voltage regulator (reg0) 5 v in 3 v out vbus sense regin vbus to 3 v power net device power net vdd from 5 v power net c8051t620/621/320/321/322/323 62 rev. 1.1 11.2. voltage regulator (reg1) under default conditions, th e internal reg1 regulator will remain on when the device enters stop mode. this allows any enabled reset source to generate a reset for the device and bring the device out of stop mode. for additional power savings, the stopcf bit can be used to shut down the regulator and the inter- nal power network of the device when the part enters stop mode. when stopcf is set to 1, the rst pin and a full power cycle of the device are the only methods of generating a reset. reg1 offers an additional low power mode intended fo r use when the device is in suspend mode. this low power mode should not be used during normal operation or if the reg0 voltage regulator is disabled. see table 7.5 for normal and low power mode supply curr ent specifications. the reg1 mode selection is con- trolled via the reg1md bi t in register reg01cn. important note: at least 12 clock instructions must occur after placing reg1 in low power mode before the internal high frequency oscillator is susp ended (oscicn.5 = 1b). rev. 1.1 63 c8051t620/621/320/321/322/323 sfr address = 0xc9 sfr definition 11.1. reg01cn: voltage regulator control b i t76543210 name reg0dis vbstat reserved reg0md stopcf reserved reg1md mpce type r/w r r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7reg0dis voltage regulator (reg0) disable. this bit enables or disables the reg0 voltage regulator. 0: voltage regulator enabled. 1: voltage regulator disabled. 6 vbstat vbus signal status. this bit indicates whether the device is connected to a usb network. 0: vbus signal currently absent (device not attached to usb network). 1: vbus signal currently present (device attached to usb network). 5 reserved must write 0b. 4reg0md voltage regulator (reg0) mode select. this bit selects the voltage regulator mode for reg0. when reg0md is set to 1, the reg0 voltage regulator operates in lower power (suspend) mode. 0: reg0 voltage regulator in normal mode. 1: reg0 voltage regulator in low power mode. 3stopcf stop mode configuration (reg1). this bit configures the reg1 regulator?s behavior when the device enters stop mode. 0: reg1 regulator is still active in stop mode. any enabled reset source will reset the device. 1: reg1 regulator is shut down in stop mode. only the rst pin or power cycle can reset the device. 2 reserved must write 0b. 1reg1md voltage regulator (reg1) mode. this bit selects the voltage regulator mode for reg1. when reg1md is set to 1, the reg1 voltage regulator operates in lower power mode. 0: reg1 voltage regulator in normal mode. 1: reg1 voltage regulator in low power mode. note: this bit should not be set to '1' if the reg0 voltage regulator is disabled. 0mpce memory power controller enable. this bit can help the system save power at slower system clock frequencies (about 2.0 mhz or less) by automatically shutting down the eprom memory betwe en clocks when information is not being fetched from th e eprom memory. this bit has no ef fect when the prefetch engine is enabled. 0: normal mode - memory pow er controller disabled ( eprom memory is always on). 1: low power mode - memory power controller enabled (eprom turns on/off as needed). note: if an external clock source is used with the memory power controller enabled, and the clock frequency changes from slow (< 2.0 mhz) to fast (> 2.0 mhz), up to 20 clocks may be "skipped" to ensure that the eprom power is stable before reading memory. c8051t620/621/320/321/322/323 64 rev. 1.1 12. cip-51 microcontroller the mcu system controller core is the cip-51 microcon troller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemble rs and compilers can be used to develop soft- ware. the mcu family has a superset of all the peri pherals included with a standard 8051. the cip-51 also includes on-chip debug hardware (see descriptio n in section 30), and interfaces directly with the ana- log and digital subsystems providing a complete data acqu isition or control-system so lution in a single inte- grated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (s ee figure 12.1 for a block diagram). the cip-51 includes the following features: performance the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan- dard 8051 architecture. in a standar d 8051, all instructions except for mul and div take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 mhz. by contrast, the cip-51 core executes 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles. figure 12.1. cip-51 block diagram ? fully compatible with mc s-51 instruction set ? 48 mips peak throughput with 48 mhz clock ? 0 to 48 mhz clock frequency ? extended interrupt handler ? reset input ? power management modes ? on-chip debug logic ? program and data memory security data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram d8 stack pointer d8 rev. 1.1 65 c8051t620/621/320/321/322/323 with the cip-51's maximum system clock at 48 mhz, it has a peak throughput of 48 mips. the cip-51 has a total of 109 instructions. the table below shows the to tal number of instructions that require each execu- tion time. programming and debugging support in-system programming of the eprom program memory and communication with on-chip debug support logic is accomplished via the silicon l abs 2-wire development interface (c2). the on-chip debug support logic facilitates full speed in-circuit debugging, a llowing the setting of hardware breakpoints, starting, stopping and single stepping th rough program execution (including interrupt service routines), examination of the program's call stack, a nd reading/writing the conten ts of registers and mem- ory. this method of on-chip debugging is completely non-intrusive, requiring no ram, stack, timers, or other on-chip resources. c2 details can be foun d in section ?30. c2 interface? on page 282. the cip-51 is support ed by development tools from silicon labs and third party vendors. silicon labs pro- vides an integrated development environment (ide) in cluding editor, debugger and programmer. the ide's debugger and programmer interface to the cip-51 via the c2 interface to provide fast and efficient in-sys- tem device programming and debugging. third party macro assemblers and c compilers are also avail- able. 12.1. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruc- tion set. standard 8051 development tools can be used to develop software for the cip-51. all cip-51 instructions are the binary and fu nctional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, in struction timing is different than that of the stan- dard 8051. 12.1.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instruction timings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instruct ions take one less clock cycle to complete when the branch is not taken as oppo sed to when the branch is taken. table 12.1 is the cip-51 instruction set summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. clocks to execute 1 2 2/4 3 3/5 4 5 4/6 6 8 number of instructions 2650510752121 c8051t620/621/320/321/322/323 66 rev. 1.1 table 12.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract imme diate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 rev. 1.1 67 c8051t620/621/320/321/322/323 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 table 12.1. cip-51 instruction set summary(continued) mnemonic description bytes clock cycles c8051t620/621/320/321/322/323 68 rev. 1.1 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/4 jnc rel jump if carry is not set 2 2/4 jb bit, rel jump if direct bit is set 3 3/5 jnb bit, rel jump if direct bit is not set 3 3/5 jbc bit, rel jump if direct bit is set and clear bit 3 3/5 program branching acall addr11 absolute subroutine call 2 4 lcall addr16 long subroutine call 3 5 table 12.1. cip-51 instruction set summary(continued) mnemonic description bytes clock cycles rev. 1.1 69 c8051t620/621/320/321/322/323 ret return from subroutine 1 6 reti return from interrupt 1 6 ajmp addr11 absolute jump 2 4 ljmp addr16 long jump 3 5 sjmp rel short jump (relative address) 2 4 jmp @a+dptr jump indirect relative to dptr 1 4 jz rel jump if a equals zero 2 2/4 jnz rel jump if a does not equal zero 2 2/4 cjne a, direct, rel compare direct byte to a and jump if not equal 3 3/5 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/5 cjne rn, #data, rel compare immediate to register and jump if not equal 33/5 cjne @ri, #data, rel compare immediate to indirect and jump if not equal 34/6 djnz rn, rel decrement regist er and jump if not zero 2 2/4 djnz direct, rel decrement direct byte and jump if not zero 3 3/5 nop no operation 1 1 table 12.1. cip-51 instruction set summary(continued) mnemonic description bytes clock cycles c8051t620/621/320/321/322/323 70 rev. 1.1 12.2. cip-51 re gister descriptions following are descriptions of sfrs related to the operati on of the cip-51 system controller. reserved bits should always be written to the value indicated in the sfr description. future product versions may use these bits to implemen t new features in which case the reset value of the bit will be the indicated value, selecting the feature's default state. detailed descriptions of the remaining sfrs are included in the sec- tions of the datasheet associated with their corresponding system function. notes on registers, operands and addressing modes: rn - register r0?r7 of the curr ently selected register bank. @ri - data ram location addressed indirectly through r0 or r1. rel - 8-bit, signed (two?s complement) offset relative to the first byte of the following instruction. used by sjmp and all conditional jumps. direct - 8-bit internal data location?s address. this could be a direct-access data ram location (0x00? 0x7f) or an sfr (0x80?0xff). #data - 8-bit constant #data16 - 16-bit constant bit - direct-accessed bit in data ram or sfr addr11 - 11-bit destination address used by acall and ajmp. the destination mu st be within the same 2 kb page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by lcall a nd ljmp. the destination may be anywhere within the 8 kb program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980. rev. 1.1 71 c8051t620/621/320/321/322/323 sfr address = 0x82 sfr address = 0x83 sfr definition 12.1. dpl: data pointer low byte bit76543210 name dpl[7:0] type r/w reset 00000000 bit name function 7:0 dpl[7:0] data pointer low. the dpl register is the low byte of the 16-bit dptr. sfr definition 12.2. dph: data pointer high byte bit76543210 name dph[7:0] type r/w reset 00000000 bit name function 7:0 dph[7:0] data pointer high. the dph register is the high byte of the 16-bit dptr. c8051t620/621/320/321/322/323 72 rev. 1.1 sfr address = 0x81 sfr address = 0xe0; bit-addressable sfr address = 0xf0; bit-addressable sfr definition 12.3. sp: stack pointer bit76543210 name sp[7:0] type r/w reset 00000111 bit name function 7:0 sp[7:0] stack pointer. the stack pointer holds the location of the to p of the stack. the stack pointer is incre- mented before every push operation. the sp register defaults to 0x07 after reset. sfr definition 12.4. acc: accumulator bit76543210 name acc[7:0] type r/w reset 00000000 bit name function 7:0 acc[7:0] accumulator. this register is the accumulator for arithmetic operations. sfr definition 12.5. b: b register bit76543210 name b[7:0] type r/w reset 00000000 bit name function 7:0 b[7:0] b register. this register serves as a second accumu lator for certain arithmetic operations. rev. 1.1 73 c8051t620/621/320/321/322/323 sfr address = 0xd0; bit-addressable sfr definition 12.6. psw : program status word bit76543210 name cy ac f0 rs[1:0] ov f1 parity type r/w r/w r/w r/w r/w r/w r reset 00000000 bit name function 7cy carry flag. this bit is set when the last arithmetic oper ation resulted in a carry (addition) or a bor- row (subtraction). it is cleared to logi c 0 by all other arithmetic operations. 6ac auxiliary carry flag. this bit is set when the last arithmetic operat ion resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to logic 0 by all other arith- metic operations. 5f0 user flag 0. this is a bit-addressable, general purp ose flag for use under software control. 4:3 rs[1:0] register bank select. these bits select which register bank is used during register accesses. 00: bank 0, addresses 0x00-0x07 01: bank 1, addresses 0x08-0x0f 10: bank 2, addresses 0x10-0x17 11: bank 3, addresses 0x18-0x1f 2ov overflow flag. this bit is set to 1 under the following circumstances: ?? an add, addc, or subb instruction causes a sign-change overflow. ?? a mul instruction results in an overflow (result is greater than 255). ?? a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, a ddc, subb, mul, and div instructions in all other cases. 1f1 user flag 1. this is a bit-addressable, general purp ose flag for use under software control. 0parity parity flag. this bit is set to logic 1 if the sum of the ei ght bits in the accumulator is odd and cleared if the sum is even. c8051t620/621/320/321/322/323 74 rev. 1.1 13. prefetch engine the c8051t620/621/320/321/322/323 fa mily of devices incorporate a 2-byte prefetch engine. because the access time of the eprom memory is 40 ns, and th e minimum instruction time is roughly 20 ns, the prefetch engine is necessary for full-speed code ex ecution. instructions are read from eprom memory two bytes at a time by the prefetch engine and given to the cip-51 pr ocessor core to execute. when run- ning linear code (code without any jumps or branches), th e prefetch engine allows instructions to be exe- cuted at full speed. when a code branch occurs, the processor may be stalled for up to two clock cycles while the next set of code bytes is retrieved from eprom memory. note: the prefetch engine should be disabled when the device is in suspend mode to save power. sfr address = 0xaf sfr definition 13.1. pfe0cn: prefetch engine control bit76543210 name pfen type rrr/wrrrrr reset 00100000 bit name function 7:6 unused unused. read = 00b, write = don?t care. 5pfen prefetch enable. this bit enables the prefetch engine. 0: prefetch engine is disabled. 1: prefetch engine is enabled. 4:0 unused unused. read = 00 000b. write = don?t care. rev. 1.1 75 c8051t620/621/320/321/322/323 14. comparator0 and comparator1 c8051t620/621/320/321/322/323 de vices include two on-chip programmable voltage comparators: comparator0 is shown in figure 14.1, comparator1 is shown in figure 14.2. the two comparators operate identically with the following except ions: (1) their input selections differ as described in section ?14.1. comparator multiplexers? on page 82; (2) comparator0 can be used as a reset source. the comparators offer programmable response time and hysteresis, an analog in put multiplexer, and two outputs that are optionally available at the port pins : a synchronous ?latched? output (cp0 or cp1), or an asynchronous ?raw? output (cp0a or cp1a). the asyn chronous signals are available even when the sys- tem clock is not active. this allows the comparators to operate and generate an output with the device in stop mode. when assigned to a port pin, the comparator outputs may be configured as open drain or push-pull (see section ?22.4. port i/o initialization? on page 141). comparator0 may also be used as a reset source (see section ?20.5. comparator0 reset? on page 119). the comparator inputs are selected by the compar ator input multiplexers, as detailed in section ?14.1. comparator multiplexers? on page 82. figure 14.1. comparator0 functional block diagram vdd reset decision tree + - crossbar q q set clr d q q set clr d (synchronizer) gnd cp0 + cp0 - cpt0md cp0rie cp0fie cp0md1 cp0md0 cp0 cp0a cp0 interrupt 0 1 0 1 cp0rif cp0fif 0 1 cp0en 0 1 ea comparator input mux cpt0cn cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 c8051t620/621/320/321/322/323 76 rev. 1.1 figure 14.2. comparator1 functional block diagram the comparator output can be polled in software, used as an interrupt source, and/or routed to a port pin. when routed to a port pin, the comp arator output is available asynch ronous or synchronous to the system clock; the asynchronous output is available even in stop mode (with no system clock active). when dis- abled, the comparator output (if assigned to a port i/o pin via the crossbar) defaults to the logic low state, and the power supply to the comparat or is turned off. see section ?22.3. priority crossbar decoder? on page 137 for details on configuring comparator outputs via the digital crossbar. comparator inputs can be externally driven from ?0.25 v to (v dd ) + 0.25 v without damage or upset. the complete comparator elec- trical specifications are given in section ?7. electrical characteristics? on page 33. the comparator response time may be configured in software via the cptnmd registers (see sfr defini- tion 14.2 and sfr definition 14.4). selecting a longer response time reduces the comparator supply cur- rent. vdd + - crossbar q q set clr d q q set clr d (synchronizer) gnd cp1 + cp1 - cpt1md cp1rie cp1fie cp1md1 cp1md0 cp1 cp1a cp1 interrupt 0 1 0 1 cp1rif cp1fif 0 1 cp1en 0 1 ea comparator input mux cpt1cn cp1en cp1out cp1rif cp1fif cp1hyp1 cp1hyp0 cp1hyn1 cp1hyn0 rev. 1.1 77 c8051t620/621/320/321/322/323 figure 14.3. comparator hysteresis plot the comparator hysteresis is software-programm able via its comparator control register cptncn (for n = 0 or 1). the user can program both the amount of hysteresis voltage (refer red to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. the comparator hysteresis is programmed using bits3 ? 0 in the comparator control register cptncn (shown in sfr definition 14.1). the amount of negative hysteresis voltage is determined by the settings of the cpnhyn bits. settings of 20, 10 or 5 mv of no minal negative hysteresis can be programmed, or nega- tive hysteresis can be disabled. in a similar way, the amount of positive hysteresis is determined by the setting the cpnhyp bits. comparator interrupts can be genera ted on both rising-e dge and falling-edge output transitions. (for inter- rupt enable and priority control, see section ?17.1. mcu interrupt sources and vectors? on page 96). the cpnfif flag is set to logic 1 upo n a comparator falling-edge occurrence , and the cpnrif flag is set to logic 1 upon the comparator rising-edge occurrence. once set, these bits remain set until cleared by soft- ware. the comparator rising-edge interrupt mask is e nabled by setting cpnrie to a logic 1. the compar- ator falling-edge interrupt mask is e nabled by setting cpnfie to a logic 1. the output state of the comparator can be obtained at any time by reading the cpnout bit. the compar- ator is enabled by setting the cpnen bit to logic 1, and is disabled by clearing this bit to logic 0. note that false rising ed ges and falling edges can be detected when the comparator is fi rst powered on or if changes are made to the hy steresis or response time control bits. therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a sh ort time after the comparator is enabled or its mode bits have been changed. positive hysteresis voltage (programmed with cpnhyp bits) negative hysteresis voltage (programmed by cpnhyn bits) vin- vin+ inputs circuit configuration + _ cpn+ cpn- cpn vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol c8051t620/621/320/321/322/323 78 rev. 1.1 sfr address = 0x9b sfr definition 14.1. cpt0 cn: comparator0 control bit76543210 name cp0en cp0out cp0rif cp0fif cp0hyp[1:0] cp0hyn[1:0] type r/w r r/w r/w r/w r/w reset 00000000 bit name function 7 cp0en comparator0 enable bit. 0: comparator0 disabled. 1: comparator0 enabled. 6cp0out comparator0 output state flag. 0: voltage on cp0+ < cp0 ? . 1: voltage on cp0+ > cp0 ? . 5cp0rif comparator0 rising-edge flag. must be cleared by software. 0: no comparator0 rising edge has occurred since this flag was last cleared. 1: comparator0 rising edge has occurred. 4cp0fif comparator0 falling-edge flag. must be cleared by software. 0: no comparator0 falling-edge has occu rred since this flag was last cleared. 1: comparator0 falling- edge has occurred. 3:2 cp0hyp[1:0] comparator0 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. 1:0 cp0hyn[1:0] comparator0 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv. rev. 1.1 79 c8051t620/621/320/321/322/323 sfr address = 0x9d sfr definition 14.2. cpt0md: comparator0 mode selection bit76543210 name cp0rie cp0fie cp0md[1:0] type rrr/wr/wrr r/w reset 00000010 bit name function 7:6 unused unused. read = 00b, write = don?t care. 5cp0rie comparator0 rising-edge interrupt enable. 0: comparator0 rising-edge interrupt disabled. 1: comparator0 rising-edge interrupt enabled. 4cp0fie comparator0 falling-edge interrupt enable. 0: comparator0 falling-edge inte rrupt disabled. 1: comparator0 falling-edge inte rrupt enabled. 3:2 unused unused. read = 00b, write = don?t care. 1:0 cp0md[1:0] comparator0 mode select. these bits affect the response time and power consumption for comparator0. 00: mode 0 (fastest response time, highest power consumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power consumption) c8051t620/621/320/321/322/323 80 rev. 1.1 sfr address = 0x9a sfr definition 14.3. cpt1 cn: comparator1 control bit76543210 name cp1en cp1out cp1rif cp1fif cp1hyp[1:0] cp1hyn[1:0] type r/w r r/w r/w r/w r/w reset 00000000 bit name function 7 cp1en comparator1 enable bit. 0: comparator1 disabled. 1: comparator1 enabled. 6cp1out comparator1 output state flag. 0: voltage on cp1+ < cp0 ? . 1: voltage on cp1+ > cp0 ? . 5cp1rif comparator1 rising-edge flag. must be cleared by software. 0: no comparator1 rising edge has occurred since this flag was last cleared. 1: comparator1 rising edge has occurred. 4cp1fif comparator1 falling-edge flag. must be cleared by software. 0: no comparator1 falling-edge has occu rred since this flag was last cleared. 1: comparator1 falling- edge has occurred. 3:2 cp1hyp[1:0] comparator1 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. 1:0 cp1hyn[1:0] comparator1 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv. rev. 1.1 81 c8051t620/621/320/321/322/323 sfr address = 0x9c sfr definition 14.4. cpt1md: comparator1 mode selection bit76543210 name cp1rie cp1fie cp1md[1:0] type rrr/wr/wrr r/w reset 00000010 bit name function 7:6 unused unused. read = 00b, write = don?t care. 5cp1rie comparator1 rising-edge interrupt enable. 0: comparator1 rising-edge interrupt disabled. 1: comparator1 rising-edge interrupt enabled. 4cp1fie comparator1 falling-edge interrupt enable. 0: comparator1 falling-edge inte rrupt disabled. 1: comparator1 falling-edge inte rrupt enabled. 3:2 unused unused. read = 00b, write = don?t care. 1:0 cp1md[1:0] comparator1 mode select. these bits affect the response time and power consumption for comparator1. 00: mode 0 (fastest response time, highest power consumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power consumption) c8051t620/621/320/321/322/323 82 rev. 1.1 14.1. comparator multiplexers c8051t620/621/320/321/322/323 devices include an analog input multiplexer to connect port i/o pins to the comparator inputs. the comparator inputs are sele cted in the cptnmx registers (sfr definition 14.5 and sfr definition 14.6). the cmxnp2 ? cmxnp0 bits select the compar ator positive input; the cmxnn2 ? cmxnn0 bits select the co mparator negative input. important note about comparator inputs: the port pins selected as comparator inputs should be con- figured as analog inputs in their associated port co nfiguration register, and configured to be skipped by the crossbar (for details on port configuration, see se ction ?22.6. special function registers for accessing and configuring port i/o? on page 146). figure 14.4. comparator input multiplexer block diagram + - cp1 + p1.2 cp1 - cpt1mx cmx1n2 cmx1n1 cmx1n0 cmx1p2 cmx1p1 cmx1p0 p1.6 p2.2 p0.4 gnd vdd p1.3 p1.7 p2.3 p0.5 + - cp0 + p1.0 cp0 - cpt0mx cmx0n2 cmx0n1 cmx0n0 cmx0p2 cmx0p1 cmx0p0 p1.4 p2.0 p2.4 p0.0 gnd vdd p1.1 p1.5 p2.1 p2.5 p0.1 rev. 1.1 83 c8051t620/621/320/321/322/323 sfr address = 0x9f sfr definition 14.5. cpt0mx: comparator0 mux selection bit76543210 name cmx0n[2:0] cmx0p[2:0] type rr/wrr/w reset 00000000 bit name function 7 unused unused. read = 0b; write = don?t care. 6:4 cmx0n[2:0] comparator0 negative input mux selection. 000: p1.1 001: p1.5 010: p2.1 011: p2.5 100: p0.1 101-111: reserved 3 unused unused. read = 0b; write = don?t care. 2:0 cmx0p[2:0] comparator0 positive input mux selection. 0000: p1.0 0001: p1.4 0010: p2.0 0011: p2.4 0100: p0.0 101?111: reserved c8051t620/621/320/321/322/323 84 rev. 1.1 sfr address = 0x9e sfr definition 14.6. cpt1mx: comparator1 mux selection bit76543210 name cmx1n[2:0] cmx1p[2:0] type rr/wrr/w reset 00000000 bit name function 7 unused unused. read = 0b; write = don?t care. 6:4 cmx1n[2:0] comparator1 negative input mux selection. 000: p1.3 001: p1.7 010: p2.3 011: reserved 100: p0.5 101-111: reserved 3 unused unused. read = 0b; write = don?t care. 2:0 cmx1p[2:0] comparator1 positive input mux selection. 000: p1.2 001: p1.6 010: p2.2 011: reserved 100: p0.4 101-111: reserved rev. 1.1 85 c8051t620/621/320/321/322/323 15. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different instruction types. the memory organization of the c8051t620/621/320/321/32 2/323 device family is shown in figure 15.1 figure 15.1. memory map 15.1. program memory the cip-51 core has a 64 kb program memory spac e. the c8051t620/621/320/321/322/323 implements 16384 bytes of this program memory space as in- system byte-programmable eprom organized in a con- tiguous block from addresses 0x0000 to 0x3fff. note: 512 bytes (0x3e00 ? 0x3fff) of this memory are reserved for factory use and are not available for user program storage. c2 regist er definition 15.2 shows the program memory maps for c8051t620/621/320/321/322/323 devices. program/data memory (eprom) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 1024 bytes (accessable using movx instruction) 0x0000 0x03ff same 1024 bytes as from 0x0000 to 0x03ff, wrapped on 1024-byte boundaries 0x0400 0xffff 16k bytes eprom memory 0x0000 reserved 0x3e00 0x3dff 0x3fff usb fifos 1024 bytes 0x0400 0x07ff c8051t620/621/320/321/322/323 86 rev. 1.1 figure 15.2. program memory map program memory is read-only from within firmware. individual program memory bytes can be read using the movc instruction. this facilitates the use of byte-programmable eprom sp ace for constant storage. 15.1.1. derivative id to distinguish between individual derivatives in t he c8051t620/621/320/321/322/323 device family, the derivative id is located at address 0x3ff9 in eprom memory. the derivative id for the devices in the c8051t620/621/320/321/32 2/323 are as follows: 15.1.2. temperature offset calibration the c8051t620/621/320/321/322/323 dev ices include a factory calibrated temperature sensor offset coef- ficient located in the eprom memory. the toffh and toffl values are located at 0x3ffb and 0x3ffa, respectively. more information on using the temperature sensor calibration values can be found in section ?9.1. calibration? on page 56. 15.1.3. serialization all c8051t620/621/320/321/322/323 devices have a fa ctory serialization locate d in eprom memory. this value is unique to each device. the serial number is located at addresses 0x3ffc-0x3fff and can be accessed like any constant array in program memory. device derivative id c8051t620 0xd0 c8051t621 0xd3 c8051t320 0xd1 c8051t321 0xd2 c8051t322 0xd4 c8051t323 0xd5 c8051t620/1 0x0000 reserved 0x3dff 15872 bytes eprom memory 0x3e00 0x3ff7 0x3ff8 security byte 0x3ffc serial number 0x3fff 0x3ffa toffh and toffl 0x3ffb 0x3ff9 derivative id rev. 1.1 87 c8051t620/621/320/321/322/323 15.2. data memory the c8051t620/621/320/321/322/323 dev ice family includes 1280 bytes of ram data memory. 256 bytes of this memory is mapped into the internal ram spac e of the 8051. 1024 bytes of this memory is on-chip ?external? memory. the data memory map is shown in figure 15.1 for reference. 15.2.1. internal ram there are 256 bytes of internal ram mapped into the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for genera l purpose registers and scratch pad memory. either direct or indirect addressing may be used to access the lower 128 bytes of data memory. locations 0x00 through 0x1f are addressable as four banks of gene ral purpose registers, each bank consisting of eight byte-wide registers. the next 16 byte s, locations 0x20 through 0x2f, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by indirect addressing. this region occupies the same address space as the special function regist ers (sfr) but is physically separate from the sfr space. the addressing mode used by an instruction when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or the sfrs. instructions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data memory. figure 15.1 illustrates th e data memory organization of the c8051t620/621/320/321/322/323. 15.2.1.1. general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as four banks of gen- eral-purpose registers. each bank consists of eigh t byte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bi ts in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see descri ption of the psw in sfr de finition 12.6). this allows fast context switching when entering subroutines and interrupt service routines. indirect addressing modes use registers r0 and r1 as index registers. 15.2.1.2. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destinat ion operands as opposed to a byte source or destina- tion). the mcs-51? assembly language allows an alternate notation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 15.2.1.3. stack a programmer's stack can be located anywhere in the 256-byte data memory. the stack area is desig- nated using the stack pointer (sp) sfr. the sp will point to the last lo cation used. the next value pushed on the stack is placed at sp+1 and then sp is incremen ted. a reset initializes the stack pointer to location 0x07. therefore, the first value pushed on the stack is placed at location 0x08, which is also the first regis- ter (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes. c8051t620/621/320/321/322/323 88 rev. 1.1 15.2.2. external ram there are 1024 bytes of on-chip ram mapped into the external data memory space. all of these address locations may be accessed using the external move instruction (movx) and the data pointer (dptr), or using movx indirect addressing mode. if the movx in struction is used with an 8-bit address operand (such as @r1), then the high byte of the 16-bit addr ess is provided by the external memory interface con- trol register (emi0cn as shown in sfr definition 15.1). for a 16-bit movx operation (@dptr), the upper 6 bits of the 16-bit external data memory address word are "don't cares" (when usbfae is cleared to 0). as a result, the 1024-byte ram is mapped modulo style over the entire 64 k external data memory address range. for example, the xram byte at address 0x0000 is shadowed at addresses 0x0400, 0x0800, 0x0c00, 0x10 00, etc. this is a useful feature when performing a linear memory fill, as th e address pointer do esn't have to be reset when reaching the ram block bound- ary. sfr address = 0xaa 15.2.3. accessing usb fifo space the c8051t620/621/320/321/322/323 include 1k of ram which functions as usb fifo space. figure 15.3 shows an expanded view of the fifo space and user xram. fifo space is normally accessed via usb fifo registers; see section ?23.5. fifo management? on page 163 for more informa- tion on accessing these fifos. the movx instruction should not be used to load or modify usb data in the fifo space. unused areas of the usb fifo space may be used as general purpose xram if necessary. the fifo block operates on the usb clock dom ain; thus the usb clock must be active when accessing fifo space. note that the number of sysclk cycles required by the movx instruction is increased when accessing usb fifo space. to access the fifo ram directly using movx instructio ns, the following conditions must be met: (1) the usbfae bit in register emi0cf must be set to '1', an d (2) the usb clock frequency must be greater than or equal to twice the sysclk (usbclk > 2 x sysclk). when this bit is set, the usb fifo space is mapped sfr definition 15.1. emi0cn: exte rnal memory interface control bit76543210 name pgsel[2:0] type rrrrrr/wr/wr/w reset 00000000 bit name function 7:3 unused unused. read = 00000b; write = don?t care 2:0 pgsel[2:0] xram page select. the emi0cn register provides the high byte of the 16-bit external data memory address when using an 8-bit movx command, effectively selecting a 256-byte page of ram. since the upper (unused) bits of the register are always zero, the pgsel determines which page of xram is accessed. for example: if emi0cn = 0x01, addr esses 0x0100 through 0x01ff will be accessed. rev. 1.1 89 c8051t620/621/320/321/322/323 into xram space at addresses 0x0400 to 0x07ff. the normal on-chip xram at the same addresses can- not be accessed when th e usbfae bit is set to 1. important note: the usb clock must be active when accessing fifo space. figure 15.3. usb fifo space and xram memory map with usbfae set to 1 on-chip xram 0x0000 endpoint0 (64 bytes) free (64 bytes) 0x0400 0x043f 0x0440 0x063f 0x0640 0x073f 0x0740 0x07bf 0x07c0 0x07ff endpoint1 (128 bytes) endpoint2 (256 bytes) endpoint3 (512 bytes) usb fifo space (usb clock domain) 0x03ff on-chip xram 0x0800 0xffff c8051t620/621/320/321/322/323 90 rev. 1.1 sfr address = 0x85 sfr definition 15.2. emi0cf: ex ternal memory configuration bit76543210 name usbfae type rr/wrrrrrr reset 00000011 bit name function 7 unused unused. read = 0b; write = don?t care 6 usbfae usb fifo access enable. 0: usb fifo ram not availabl e through movx instructions. 1: usb fifo ram available using movx in structions. the 1k of usb ram will be mapped in xram space at addresses 0x0400 to 0x07ff. the usb clock must be active and greater than or equal to twice the sysclk (usbclk > 2 x sysclk) to access this area with movx instructions. 5:0 unused unused. read = 000011b; write = don?t care rev. 1.1 91 c8051t620/621/320/321/322/323 16. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfrs). the sfrs provide control and data ex change with the c8051t620 /621/320/321/322/323's resources and peripherals. the cip-51 controller core duplicates the sfrs found in a typical 8051 imple- mentation as well as implementing additional sfrs used to configure and access the sub-systems unique to the c8051t620/621/320/321/322/323. this allows t he addition of new functionality while retaining com- patibility with the mcs-51? in struction set. table 16.1 lists the sfrs implemented in the c8051t620/621/320/321/32 2/323 device family. the sfr registers are accessed anytime the direct ad dressing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x0 or 0x8 (e.g., p0, tcon, scon0, ie, etc.) are bit- addressable as well as byte-addressable. all other sfrs are byte-addressable only. unoccupied addresses in the sfr space are reserved for future use. accessing t hese areas will have an indeterminate effect and should be avoided. refer to the corres ponding pages of the data sheet, as indicated in table 16.2, for a detailed description of each register. table 16.1. special function register (sfr) memory map f8 spi0cn pca0l pca0h pca0cpl0 pca0cph0 pca0cpl4 pca0cph4 vdm0cn f0 b p0mdin p1mdin p2mdin pca0pwm iapcn eip1 eip2 e8 adc0cn pca0cpl1 pca0cph1 pca0cpl2 pca0cph2 pca0cpl3 pca0cph3 rstsrc e0 acc xbr0 xbr1 xbr2 it01cf smod1 eie1 eie2 d8 pca0cn pca0md pca0cpm0 pca0cpm1 pca0cpm2 pca0cpm3 pca0cpm4 - d0 psw ref0cn scon1 sbuf1 p0skip p1skip p2skip usb0xcn c8 tmr2cn reg01cn tmr2rll tmr2rlh tmr2l tmr2h - smb0adm c0 smb0cn smb0cf smb0dat adc0gtl a dc0gth adc0ltl adc0lth smb0adr b8 ip clkmul p1mask amx0p adc0cf adc0l adc0h - b0 p3 oscxcn oscicn oscicl sbrll1 sbrlh1 p1mat memkey a8 ie clksel emi0cn - sbcon1 - p0mask pfe0cn a0 p2 spi0cfg spi0ckr spi0dat p0mdout p1mdout p2mdout p3mdout 98 scon0 sbuf0 cpt1cn cpt0cn cpt1md cpt0md cpt1mx cpt0mx 90 p1 tmr3cn tmr3rll tmr3rlh tmr3l tmr3h usb0adr usb0dat 88 tcon tmod tl0 tl1 th0 th1 ckcon psctl 80 p0 sp dpl dph p0mat emi0cf osclcn pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) note: sfr addresses ending in 0x0 or 0x8 are bit-addressable locations and can be used with bitwise instructions. c8051t620/621/320/321/322/323 92 rev. 1.1 table 16.2. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page acc 0xe0 accumulator 72 adc0cf 0xbc adc0 configuration 47 adc0cn 0xe8 adc0 control 49 adc0gth 0xc4 adc0 greater-than compare high 50 adc0gtl 0xc3 adc0 greater-than compare low 50 adc0h 0xbe adc0 high 48 adc0l 0xbd adc0 low 48 adc0lth 0xc6 adc0 less-than compare word high 51 adc0ltl 0xc5 adc0 less-than compare word low 51 amx0p 0xbb amux0 positive channel select 54 b 0xf0 b register 72 ckcon 0x8e clock control 241 clkmul 0xb9 clock multiplier control 127 clksel 0xa9 clock select 124 cpt0cn 0x9b comparator0 control 78 cpt0md 0x9d comparator0 mode selection 79 cpt0mx 0x9f comparator0 mux selection 83 cpt1cn 0x9b comparator1 control 80 cpt1md 0x9d comparator1 mode selection 81 cpt1mx 0x9f comparator1 mux selection 84 dph 0x83 data pointer high 71 dpl 0x82 data pointer low 71 eie1 0xe6 extended interrupt enable 1 101 eie2 0xe7 extended interrupt enable 2 103 eip1 0xf6 extended interrupt priority 1 102 eip2 0xf7 extended interrupt priority 2 104 emi0cf 0x85 external memory configuration 90 emi0cn 0xaa external memory interface control 88 iapcn 0xf5 in-application programming control 112 ie 0xa8 interrupt enable 99 ip 0xb8 interrupt priority 100 it01cf 0xe4 int0/int1 configuration 106 memkey 0xb7 eprom memory lock and key 111 rev. 1.1 93 c8051t620/621/320/321/322/323 oscicl 0xb3 internal oscillator calibration 125 oscicn 0xb2 internal oscillator control 126 osclcn 0x86 low-frequency o scillator control 128 oscxcn 0xb1 external oscillator control 132 p0 0x80 port 0 latch 147 p0mask 0xae port 0 mask configuration 145 p0mat 0x84 port 0 match configuration 145 p0mdin 0xf1 port 0 input mode configuration 148 p0mdout 0xa4 port 0 output mode configuration 148 p0skip 0xd4 port 0 skip 149 p1 0x90 port 1 latch 149 p1mask 0xba port 1mask configuration 146 p1mat 0xb6 port 1 match configuration 146 p1mdin 0xf2 port 1 input mode configuration 150 p1mdout 0xa5 port 1 output mode configuration 150 p1skip 0xd5 port 1 skip 151 p2 0xa0 port 2 latch 151 p2mdin 0xf3 port 2 input mode configuration 152 p2mdout 0xa6 port 2 output mode configuration 152 p2skip 0xd6 port 2 skip 153 p3 0xb0 port 3 latch 153 p3mdout 0xa7 port 3 output mode configuration 154 pca0cn 0xd8 pca control 276 pca0cph0 0xfc pca capture 0 high 281 pca0cph1 0xea pca capture 1 high 281 pca0cph2 0xec pca capture 2 high 281 pca0cph3 0xee pca capture 3 high 281 pca0cph4 0xfe pca capture 4 high 281 pca0cpl0 0xfb pca capture 0 low 281 pca0cpl1 0xe9 pca capture 1 low 281 pca0cpl2 0xeb pca capture 2 low 281 pca0cpl3 0xed pca capture 3 low 281 pca0cpl4 0xfd pca capture 4 low 281 pca0cpm0 0xda pca module 0 mode register 279 table 16.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page c8051t620/621/320/321/322/323 94 rev. 1.1 pca0cpm1 0xdb pca module 1 mode register 279 pca0cpm2 0xdc pca module 2 mode register 279 pca0cpm3 0xdd pca module 3 mode register 279 pca0cpm4 0xde pca module 4 mode register 279 pca0h 0xfa pca counter high 280 pca0l 0xf9 pca counter low 280 pca0md 0xd9 pca mode 277 pca0pwm 0xf4 pca pwm configuration 278 pcon 0x87 power control 115 pfe0cn 0xaf prefetch engine control 74 psctl 0x8f program store r/w control 111 psw 0xd0 program status word 73 ref0cn 0xd1 voltage reference control 58 reg01cn 0xc9 voltage regulator control 63 rstsrc 0xef reset source configuration/status 121 sbcon1 0xac uart1 baud rate generator control 225 sbrlh1 0xb5 uart1 baud rate generator high byte 225 sbrll1 0xb4 uart1 baud rate generator low byte 226 sbuf0 0x99 uart0 data buffer 215 sbuf1 0xd3 uart1 data buffer 224 scon0 0x98 uart0 control 214 scon1 0xd2 uart1 control 222 smb0adm 0xcf smbus slave address mask 199 smb0adr 0xc7 smbus slave address 198 smb0cf 0xc1 smbus configuration 194 smb0cn 0xc0 smbus control 196 smb0dat 0xc2 smbus data 200 smod1 0xe5 uart1 mode 223 sp 0x81 stack pointer 72 spi0cfg 0xa1 spi configuration 234 spi0ckr 0xa2 spi clock rate control 236 spi0cn 0xf8 spi control 235 spi0dat 0xa3 spi data 236 tcon 0x88 timer/counter control 246 table 16.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page rev. 1.1 95 c8051t620/621/320/321/322/323 th0 0x8c timer/counter 0 high 249 th1 0x8d timer/counter 1 high 249 tl0 0x8a timer/counter 0 low 248 tl1 0x8b timer/counter 1 low 248 tmod 0x89 timer/counter mode 247 tmr2cn 0xc8 timer/counter 2 control 253 tmr2h 0xcd timer/counter 2 high 255 tmr2l 0xcc timer/counter 2 low 254 tmr2rlh 0xcb timer/counter 2 reload high 254 tmr2rll 0xca timer/counter 2 reload low 254 tmr3cn 0x91 timer/counter 3control 259 tmr3h 0x95 timer/counter 3 high 261 tmr3l 0x94 timer/counter 3low 260 tmr3rlh 0x93 timer/counter 3 reload high 260 tmr3rll 0x92 timer/counter 3 reload low 260 usb0adr 0x96 usb0 indirect address 159 usb0dat 0x97 usb0 data 160 usb0xcn 0xd7 usb0 transceiver control 157 vdm0cn 0xff v dd monitor control 119 xbr0 0xe1 port i/o crossbar control 0 142 xbr1 0xe2 port i/o crossbar control 1 143 xbr2 0xe3 port i/o crossbar control 2 144 table 16.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page c8051t620/621/320/321/322/323 96 rev. 1.1 17. interrupts the c8051t620/621/320/321/322/323 include an extended interrupt system supporting a total of 18 interrupt sources with two priority levels. the allocation of interrupt sources between on-chip peripher- als and external inputs pins varies according to the specific version of the devic e. each interrupt source has one or more associated interrupt-pending flag(s) located in an sfr. when a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. if interrupts are enabled for the source, an interrupt req uest is generated when the interrupt-pending flag is set. as soon as execution of the current instructio n is complete, the cpu generates an lcall to a prede- termined address to begin execution of an interrupt se rvice routine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (the interrupt-pending flag is set to logic 1 regard- less of the interrupt's enable/disable state). each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an sfr (ie, eie1, or eie2). however, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrupt enables are recognized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. note: any instruction that clears a bit to disable an inte rrupt should be immediatel y followed by an instruc- tion that has two or more opcode bytes. using ea (global interrupt enable) as an example: // in 'c': ? ea = 0; // clear ea bit. ? ea = 0; // this is a dummy instruction with two-byte opcode. ? ; in assembly: ? clr ea ; clear ea bit. ? clr ea ; this is a dummy instruction with two-byte opcode. for example, if an interrupt is posted during the exec ution phase of a "clr ea" opcode (or any instruction which clears a bit to disable an interrupt source), an d the instruction is followed by a single-cycle instruc- tion, the interrupt may be taken. however, a read of the enable bit will return a '0' inside the interrupt ser- vice routine. when the bit-clearing op code is followed by a multi-cycle in struction, the interrupt will not be taken. some interrupt-pending flags are automatically cleare d by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interr upt request will be gen erated immediately and the cpu will re-enter the isr after the completion of the next instruction. 17.1. mcu interrupt sources and vectors the c8051t620/621/320/321/322/323 mcus support 18 in terrupt sources. software can simulate an inter- rupt by setting any interrupt-pending flag to logic 1. if interrupts are enabled for the flag, an interrupt request will be generated an d the cpu will vector to th e isr address associated with the interr upt-pending flag. mcu interrupt sources, associat ed vector addresses, priority order and control bits are summarized in table 17.1. refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). 17.1.1. interr upt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low prior- ity interrupt service routine can be pree mpted by a high priority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (ip, eip1, or eip2) used to rev. 1.1 97 c8051t620/621/320/321/322/323 configure its priority level. low priority is the default. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if bo th interrupts have the same pr iority level, a fixed prior- ity order is used to arbitrate, given in table 17.1. 17.1.2. interr upt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each sys tem clock cycle. therefore, the fa stest possible response time is 6 system clock cycles: 1 clock cycle to detect the interr upt and 5 clock cycles to complete the lcall to the isr. if an interrupt is pending when a reti is execut ed, a single instruction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new in terrupt is of greater priority) occurs when the cpu is performing an reti instruct ion followed by a div as the next instructio n. in this case, th e response time is 20 system clock cycles: 1 clock cycle to detect the in terrupt, 6 clock cycles to execute the reti, 8 clock cycles to complete the div instruction and 5 clock cycl es to execute the lcall to the isr. if the cpu is executing an isr for an interr upt with equal or higher pr iority, the new interrupt will not be serviced until the current isr completes, including the reti and following instruction. note that the cpu is stalled dur ing eprom write operations and u sb fifo movx accesses (see section ?15.2.3. accessing usb fifo space? on page 88). interrupt service latency will be in creased for interrupts occurring while the cpu is stalled. the latency for these situations will be determined by the standard interrupt service procedure (as described above) and the amount of time the cpu is stalled. 17.2. interrupt re gister descriptions the sfrs used to enable the interrupt sources and set their priority level are described in this section. refer to the data sheet section associated with a pa rticular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). c8051t620/621/320/321/322/323 98 rev. 1.1 table 17.1. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control reset 0x0000 top none n/a n/a always enabled always highest external interrupt 0 (int0 ) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) px0 (ip.0) timer 0 overflow 0x000b 1 tf0 (t con.5) y y et0 (ie.1) pt0 (ip.1) external interrupt 1 (int1 ) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) px1 (ip.2) timer 1 overflow 0x001b 3 tf1 (t con.7) y y et1 (ie.3) pt1 (ip.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) y n es0 (ie.4) ps0 (ip.4) timer 2 overflow 0x002b 5 tf2h (tmr2cn.7) tf2l (tmr2cn.6) y n et2 (ie.5) pt2 (ip.5) spi0 0x0033 6 spif (spi0cn.7) ? wcol (spi0cn.6) modf (spi0cn.5) rxovrn (spi0cn.4) y n espi0 (ie.6) pspi0 (ip.6) smb0 0x003b 7 si (smb0cn.0) y n esmb0 (eie1.0) psmb0 (eip1.0) usb0 0x0043 8 special n n eusb0 (eie1.0) pusb0 (eip1.1) adc0 window com- pare 0x004b 9 ad0wint (adc0cn.3) y n ewadc0 (eie1.2) pwadc0 (eip1.2) adc0 conversion complete 0x0053 10 ad0int (adc0cn.5) y n eadc0 (eie1.3) padc0 (eip1.3) programmable coun- ter array 0x005b 11 cf (pca0cn.7) ccfn (pca0cn.n) covf (pca0pwm.6) y n epca0 (eie1.4) ppca0 (eip1.4) comparator0 0x0063 12 cp0fif (cpt0cn.4) cp0rif (cpt0cn.5) n n ecp0 (eie1.5) pcp0 (eip1.5) comparator1 0x006b 13 cp1fif (cpt1cn.4) cp1rif (cpt1cn.5) n n ecp1 (eie1.6) pcp1 (eip1.6) timer 3 overflow 0x0073 14 tf3h (tmr3cn.7) tf3l (tmr3cn.6) nnet3 (eie1.7) pt3 (eip1.7) vbus level 0x007b 15 n/a n/a n/a evbus (eie2.0) pvbus (eip2.0) uart1 0x0083 16 ri1 (scon1.0) ti1 (scon1.1) n n es1 (eie2.1) ps1 (eip2.1) reserved 0x008b 17 n/a n/a n/a n/a n/a port match 0x0093 18 none n/a n/a emat (eie2.3) pmat (eip2.3) rev. 1.1 99 c8051t620/621/320/321/322/323 sfr address = 0xa8; bit-addressable sfr definition 17.1. ie: interrupt enable bit76543210 name ea espi0 et2 es0 et1 ex1 et0 ex0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7ea enable all interrupts. globally enables/disables all interrupts. it ov errides individual interrupt mask settings. 0: disable all interrupt sources. 1: enable each interrupt according to its individual mask setting. 6 espi0 enable serial peripheral interface (spi0) interrupt. this bit sets the masking of the spi0 interrupts. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by spi0. 5et2 enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2l or tf2h flags. 4 es0 enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable uart0 interrupt. 3et1 enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all timer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. 2 ex1 enable external interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the int1 input. 1et0 enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all timer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag. 0 ex0 enable external interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the int0 input. c8051t620/621/320/321/322/323 100 rev. 1.1 sfr address = 0xb8; bit-addressable sfr definition 17.2. ip: interrupt priority bit76543210 name pspi0 pt2 ps0 pt1 px1 pt0 px0 type r r/w r/w r/w r/w r/w r/w r/w reset 10000000 bit name function 7 unused unused. read = 1b, write = don't care. 6 pspi0 serial peripheral interface (spi 0) interrupt priority control. this bit sets the priority of the spi0 interrupt. 0: spi0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. 5pt2 timer 2 interrupt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt set to low priority level. 1: timer 2 interrupt set to high priority level. 4 ps0 uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt set to low priority level. 1: uart0 interrupt set to high priority level. 3pt1 timer 1 interrupt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt set to low priority level. 1: timer 1 interrupt set to high priority level. 2 px1 external interrupt 1 priority control. this bit sets the priority of the external interrupt 1 interrupt. 0: external interrupt 1 se t to low priority level. 1: external interrupt 1 se t to high priority level. 1pt0 timer 0 interrupt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt set to low priority level. 1: timer 0 interrupt set to high priority level. 0 px0 external interrupt 0 priority control. this bit sets the priority of the external interrupt 0 interrupt. 0: external interrupt 0 se t to low priority level. 1: external interrupt 0 se t to high priority level. rev. 1.1 101 c8051t620/621/320/321/322/323 sfr address = 0xe6 sfr definition 17.3. eie1: extended interrupt enable 1 bit76543210 name et3 ecp1 ecp0 epca0 eadc0 ewadc0 eusb0 esmb0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7et3 enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable timer 3 interrupts. 1: enable interrupt requests generated by the tf3l or tf3h flags. 6ecp1 enable comparator1 (cp1) interrupt. this bit sets the masking of the cp1 interrupt. 0: disable cp1 interrupts. 1: enable interrupt requests generated by the cp1rif or cp1fif flags. 5ecp0 enable comparator0 (cp0) interrupt. this bit sets the masking of the cp0 interrupt. 0: disable cp0 interrupts. 1: enable interrupt requests generated by the cp0rif or cp0fif flags. 4 epca0 enable programmable counte r array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pc a0 interrupts. 1: enable interrupt requests generated by pca0. 3 eadc0 enable adc0 conversion complete interrupt. this bit sets the masking of the adc0 conversion complete interrupt. 0: disable adc0 conversi on complete interrupt. 1: enable interrupt requests generated by the ad0int flag. 2ewadc0 enable window comparison adc0 interrupt. this bit sets the masking of adc0 window comparison interrupt. 0: disable adc0 window comparison interrupt. 1: enable interrupt requests generated by adc0 window compare flag (ad0wint). 1eusb0 enable usb (usb0) interrupt. this bit sets the masking of the usb0 interrupt. 0: disable all us b0 interrupts. 1: enable interrupt requests generated by usb0. 0 esmb0 enable smbus (smb0) interrupt. this bit sets the masking of the smb0 interrupt. 0: disable all smb0 interrupts. 1: enable interrupt requests generated by smb0. c8051t620/621/320/321/322/323 102 rev. 1.1 sfr address = 0xf6 sfr definition 17.4. eip1: exte nded interrupt priority 1 bit76543210 name pt3 pcp1 pcp0 ppca0 padc0 pwadc0 pusb0 psmb0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7pt3 timer 3 interrupt priority control. this bit sets the priority of the timer 3 interrupt. 0: timer 3 interrupts se t to low priority level. 1: timer 3 interrupts set to high priority level. 6pcp1 comparator1 (cp1) interru pt priority control. this bit sets the priority of the cp1 interrupt. 0: cp1 interrupt set to low priority level. 1: cp1 interrupt set to high priority level. 5pcp0 comparator0 (cp0) interru pt priority control. this bit sets the priority of the cp0 interrupt. 0: cp0 interrupt set to low priority level. 1: cp0 interrupt set to high priority level. 4 ppca0 programmable counter array (pca0) interrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. 3 padc0 adc0 conversion complete interrupt priority control. this bit sets the priority of the adc0 conversion complete interrupt. 0: adc0 conversion complete inte rrupt set to low priority level. 1: adc0 conversion complete interrupt set to high priority level. 2pwadc0 adc0 window comparator interrupt priority control. this bit sets the priority of the adc0 window interrupt. 0: adc0 window interrupt se t to low priority level. 1: adc0 window interrupt set to high priority level. 1pusb0 usb (usb0) interrupt priority control. this bit sets the priority of the usb0 interrupt. 0: usb0 interrupt set to low priority level. 1: usb0 interrupt set to high priority level. 0 psmb0 smbus (smb0) interrupt priority control. this bit sets the priority of the smb0 interrupt. 0: smb0 interrupt set to low priority level. 1: smb0 interrupt set to high priority level. rev. 1.1 103 c8051t620/621/320/321/322/323 sfr address = 0xe7 sfr definition 17.5. eie2: extended interrupt enable 2 bit76543210 name emat reserved es1 evbus type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:4 unused unused. read = 0000b, write = don't care. 3emat enable port match interrupts. this bit sets the masking of the port match event interrupt. 0: disable all port match interrupts. 1: enable interrupt requests generated by a port match. 2 reserved reserved. must write 0b. 1 es1 enable uart1 interrupt. this bit sets the masking of the uart1 interrupt. 0: disable uart1 interrupt. 1: enable uart1 interrupt. 0 evbus enable vbus level interrupt. this bit sets the masking of the vbus interrupt. 0: disable all vbus interrupts. 1: enable interrupt requests generated by vbus level sense. c8051t620/621/320/321/322/323 104 rev. 1.1 sfr address = 0xf7 sfr definition 17.6. eip2: exte nded interrupt priority 2 bit76543210 name pmat reserved ps1 pvbus type rrrrr/wr/wr/wr/w reset 00000000 bit name function 7-4 unused unused. read = 0000b, write = don't care. 3pmat port match interrupt priority control. this bit sets the priority of the port match event interrupt. 0: port match interrupt se t to low priority level. 1: port match interrupt se t to high priority level. 2 reserved reserved. must write 0b. 1 ps1 uart1 interrupt priority control. this bit sets the priority of the uart1 interrupt. 0: uart1 interrupt set to low priority level. 1: uart1 interrupt set to high priority level. 0 pvbus vbus level interrupt priority control. this bit sets the priority of the vbus interrupt. 0: vbus interrupt set to low priority level. 1: vbus interrupt set to high priority level. rev. 1.1 105 c8051t620/621/320/321/322/323 17.3. int0 and int1 external interrupt sources the int0 and int1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. the in0pl (int0 polarity) and in1pl (int1 polarity) bits in the it01cf register select active high or active low; the it0 and it1 bits in tcon (section ?28.1. timer 0 and timer 1? on page 242) select level or edge sensitive. the table below lis ts the possible configurations. int0 and int1 are assigned to port pins as defined in the it01cf register (see sfr definition 17.7). note that int0 and int0 port pin assignments are independent of any crossbar assignments. int0 and int1 will monitor their assigned port pins wit hout disturbing the peripheral that was assigned the port pin via the crossbar. to assign a port pin only to int0 and/or int1 , configure the crossbar to skip the selected pin(s). this is accomplished by setting the a ssociated bit in register pnskip (see section ?22.3. priority crossbar decoder? on page 137 for complete details on configuring the crossbar). ie0 (tcon.1) and ie1 (tcon.3) serve as the interrupt-pending flags for the int0 and int1 external inter- rupts, respectively. if an int0 or int1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the cpu ve ctors to the isr. when configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (in0pl or in1pl); th e flag remains logic 0 while the input is inactive. the external interrupt source must hold the input active until the interrupt request is recognized. it must then deactivate the interrupt request befor e execution of the isr completes or another interrup t request will be generated. it0 in0pl int0 interrupt it1 in1pl int1 interrupt 1 0 active low, edge sensitive 1 0 active low, edge sensitive 1 1 active high, edge sensitive 1 1 active high, edge sensitive 0 0 active low, level sensitive 0 0 active low, level sensitive 0 1 active high, level sensitive 0 1 active high, level sensitive c8051t620/621/320/321/322/323 106 rev. 1.1 sfr address = 0xe4 sfr definition 17.7. it01cf: int0 /int1 configuration o bit76543210 name in1pl in1sl[2:0] in0pl in0sl[2:0] type r/w r/w r/w r/w reset 00000001 bit name function 7in1pl int1 polarity. 0: int1 input is active low. 1: int1 input is active high. 6:4 in1sl[2:0] int1 port pin se lection bits. these bits select which port pin is assigned to int1 . note that this pin assignment is independent of the crossbar; int1 will monitor the assigned po rt pin without disturb- ing the peripheral that has been assigned t he port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7 3in0pl int0 polarity. 0: int0 input is active low. 1: int0 input is active high. 2:0 in0sl[2:0] int0 port pin se lection bits. these bits select which port pin is assigned to int0 . note that this pin assignment is independent of the crossbar; int0 will monitor the assigned po rt pin without disturb- ing the peripheral that has been assigned t he port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7 rev. 1.1 107 c8051t620/621/320/321/322/323 18. program memory (eprom) c8051t620/621/320/321/322/323 devi ces include 16 kb of on-chip byte-programmable eprom for pro- gram code storage. the eprom memory can be programmed via the c2 debug and programming inter- face when a special programming voltage is applied to the v pp pin. additionally, eprom bytes can be programmed in system using an external capacitor on the v pp pin. each location in eprom memory is programmable only once (i.e. non-erasable). table 7.6 on page 36 shows the eprom specifications. 18.1. programming the eprom memory 18.1.1. eprom programming over the c2 interface programming of the eprom memory is accomplished through the c2 pr ogramming and debug interface. when creating hardware to program the eprom, it is necessary to follow the programming steps listed below. please refer to the ?c2 interface specificatio n? available at http://www.s ilabs.com for details on communicating via the c2 in terface. section ?30. c2 interface? on page 282 has information about c2 reg- ister addresses for the c8051t620/621/320/321/322/323. 1. reset the device using the rst pin . 2. wait at least 20 ms before sending th e first c2 command. 3. place the device in core reset: write 0x04 to the devctl register . 4. set the device to program mode (1st step): write 0x40 to the epctl register . 5. set the device to program mode (2nd step): write 0x4a to the epctl register . note: devices with a date code prior to 1040 should write 0x58 to the epctl register. 6. apply the v pp programming voltage . 7. write the first eprom address for programming to epaddrh and epaddrl . 8. write a data byte to epdat . epaddrh:l will increment by 1 after this write. 9. poll the epbusy bit using a c2 address read co mmand. note: if eperror is set at this time, the write operation failed. 10.if programming is not finished, return to step 8 to write the next address in sequence, or return to step 7 to program a new address. 11. remove the v pp programming voltage . 12.remove program mode (1st step): write 0x40 to the epctl register . 13.remove program mode (2nd step): write 0x00 to the epctl register . 14.reset the device: write 0x02 and then 0x00 to the devctl register . important note 1: there is a finite amount of time which v pp can be applied without damaging the device, which is cumulative over the life of the device. refer to table 7.1 on page 33 for the v pp timing specifica- tion. c8051t620/621/320/321/322/323 108 rev. 1.1 18.1.2. eprom in-appli cation programming the eprom of the c8051t620/621/320/321/322/323 de vices has an in-application programming option. in-application programming will be much slower t han normal programming where the v pp programming voltage is applied to the v pp pin, but it allows a small number of bytes to be programmed anywhere in the non-reserved areas of the eprom. in order to use this option, v io must be within a specific range and a capacitor must be connected externally to the v pp pin. refer to section ?7. electrical characteristics? on page 33 for the acceptable range of values for v io and the capacitor on the v pp pin. bytes in the eprom memory must be written one byte at a time. an eprom write will be performed after each movx write instruction. the recommended proc edure for writing to the eprom is as follows: 1. disable interrupts . 2. change the core clock to 25 mhz or less. 3. enable the vdd monitor. write 0x80 to vdm0cn. 4. enable the vdd monitor as a reset source. write 0x02 to rstsrc. 5. disable the prefetch engine. write 0x00 to the pfe0cn register. 6. set the vpp pin to an open -drain configuration, with a ?1? in the port latch. 7. set the pswe bit (register psctl). 8. write the first key code to memkey: 0xa5 . 9. write the second key code to memkey: 0xf1 . 10.enable in-application programming. write 0x80 to the iapcn register. 11. using a movx write instruction, write a single data byte to the desired location. 12.disable in-application eprom programming. write 0x00 to the iapcn register. 13. clear the pswe bit . 14.re-enable the prefetch engine. write 0x20 to the pfe0cn register. 15.delay for at least 1 us. 16.disable the programming hardware. write 0x40 to the iapcn register. 17. restore the core clock (if changed in step 2) 18. re-enable interrupts . steps 8?11 must be repeated for each byte to be written. when an application uses the in-application programming feature, the v pp pin must be set to open-drain mode, with a ?1? in the port latch. the pin can still be used a as a general-purpose i/o pin if the program- ming circuitry of the pin is disabled after all writes are completed by using the iaphwd bit in the iapcn register (iapcn.6). it is not necessary to disable the programming hardware if the in-application program- ming feature has not been used. important note: software should delay for at least 1 s after the last eprom write before setting the iaphwd bit. rev. 1.1 109 c8051t620/621/320/321/322/323 18.2. security options the c8051t620/621/320/321/322/323 de vices provide security options to prevent unauthorized viewing of proprietary program code and constants. a security by te stored at location 0x3ff8 in the eprom address space can be used to lock the program memory from being read or written across the c2 interface. the lock byte can always be read regardless of the security settings. table 18.1 show s the security byte decod- ing. refer to ?figure 15.2. program memory map? on page 86 for the location of the security byte in eprom memory. important note: once the security byte has been written, there are no means of unlocking the device. locking memory from write access should be performe d only after all other code has been successfully programmed to memory. 18.3. eprom writing guidelines any system which contains routines which write eprom memory from software involves some risk that the write routines will execute unintent ionally if the cpu is operating out side its specifi ed operating range of v dd , system clock frequency, or temperature. this a ccidental execution of eprom modifying code can result in alteration of eprom memory contents causing a system failure. the following guidelines are recommended for any sy stem which contains routines which write eprom memory from code. 18.3.1. vdd maintenance and the vdd monitor 1. if the system power supply is subject to voltage or current "spikes," add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the absolute maximum ratings table are not exceeded. 2. make certain that the minimum v dd rise time specification of 1 ms is met. if the system cannot meet this rise time specificati on, then add an external v dd brownout circuit to the rst pin of the device that holds the device in reset until v dd reaches v rst and re-asserts rst if v dd drops below v rst . 3. enable the on-chip v dd monitor and enable the v dd monitor as a reset source as early in code as possible. this should be the first set of instructio ns executed after the reset vector. for 'c'-based systems, this will involve modifying the startup code adde d by the 'c' compiler. see your compiler documentation for more details. make certain that th ere are no delays in software between enabling the v dd monitor and enabling the v dd monitor as a reset source. note: both the vdd monitor and the vdd monitor reset source must be enabled to write the eprom without generating an eprom error device reset. 4. as an added precaution, explicitly enable the v dd monitor and enable the v dd monitor as a reset source inside the functions t hat write eprom memory. the v dd monitor enable instructions should be placed just after the instruction to set pswe to a 1, but before the eprom write operation instruction. 5. make certain that all writes to the rstsrc (reset sources) register use di rect assignment operators and explicitly do not use the bit-wise operators (such as and or or). for example,"rstsrc = 0x02" is correct. "rstsrc |= 0x02" is incorrect. 6. make certain that all writes to the rstsrc register explicitly set the porsf bi t to a 1. areas to check are initialization code which enables other reset sources, such as the missing clock detector, for table 18.1. security byte decoding bits description 7?4 write lock: clearing any of these bits to logic 0 prevents all code memory from being written across the c2 interface. 3?0 read lock: clearing any of these bits to logic 0 prevents all code memory from being read across the c2 interface. c8051t620/621/320/321/322/323 110 rev. 1.1 example, and instructions which force a software reset. a global search on "rstsrc" can quickly verify this. 18.3.2. pswe maintenance 7. reduce the number of places in code where the pswe bit (psctl.0) is set to a 1. there should be exactly one routine in code that sets pswe to a 1 to write eprom bytes. 8. minimize the number of variable accesses while pswe is set to a 1. handle pointer address updates and loop variable maintenance outside the "pswe = 1;... pswe = 0;" area. 9. disable interrupts prior to setting pswe to a '1' and leave them disabled until after pswe has been reset to '0'. any interrupt s posted during the eprom write operat ion will be serviced in priority order after the eprom operation has been completed and interrupts have been re-enabled by software. 10.make certain that the eprom write pointer variables are not located in xram. see your compiler documentation for instructions regarding how to exp licitly locate variables in different memory areas. 11. add address bounds checking to the routines that write eprom memory to ensure that a routine called with an illegal address does not result in modifi cation of the eprom. 18.3.3. system clock 12.if operating from an external crystal, be advised th at crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. if the system is operating in an electrically noisy environment, use the internal oscillator or an external cmos clock. 13.if operating from the external osc illator, switch to the in ternal oscillator during eprom write operations. the external oscillator can continue to run, and the cpu can swit ch back to the exte rnal oscillator after the eprom operation has completed. 18.4. program memory crc a crc engine is included on-chip which provides a me ans of verifying eprom contents once the device has been programmed. the crc engine is available for eprom verification even if the device is fully read and write locked, allowing for verification of code contents at any time. the crc engine is operated through the c2 debug and programming interface, an d performs 16-bit crcs on individual 256-byte blocks of program memory, or a 32-bit crc on the entire memory space. to prevent hacking and extrapolation of securi ty-locked source code, the crc engi ne will only allow crcs to be per- formed on contiguous 256-byte blocks beginning on 256-byte boundaries (lowest 8-bits of address are 0x00). for example, the crc engine can perform a crc for locations 0x0400 through 0x04ff, but it can- not perform a crc for locations 0x0401 through 0x0500, or on block sizes sm aller or larg er than 256 bytes. 18.4.1. performing 32-bit cr cs on full eprom content a 32-bit crc on the entire eprom space is initiated by writing to the crc1 byte over the c2 interface. the crc calculation begins at a ddress 0x0000, and ends at the en d of user eprom space. the epbusy bit in register c2add will be set during the crc operation, and cleared once th e operation is complete. the 32-bit results will be available in the crc3-0 registers. crc3 is the msb, and crc0 is the lsb. the polynomial used for the 32-bit crc ca lculation is 0x04c11db7 . note: if a 16-bit crc has been performed since the last device reset, a device reset should be initiated before performing a 32-bit crc operation. 18.4.2. performing 16-bit crcs on 256-byte eprom blocks a 16-bit crc of individual 256-byte blocks of eprom ca n be initiated by writing to the crc0 byte over the c2 interface. the value written to crc0 is the high byte of the beginni ng address for th e crc. for exam- ple, if crc0 is written to 0x02, the crc will be pe rformed on the 256-bytes beginning at address 0x0200, and ending at address 0x2ff. the epbusy bit in regi ster c2add will be set durin g the crc operation, and cleared once the operation is complete. the 16-bit results will be ava ilable in the crc1-0 registers. crc1 is the msb, and crc0 is the lsb. the polynom ial for the 16-bit crc calculation is 0x1021. rev. 1.1 111 c8051t620/621/320/321/322/323 sfr address = 0x8f sfr address = 0xb7 sfr definition 18.1. psctl: program store r/w control bit76543210 name pswe type rrrrrrrr/w reset 00000000 bit name function 7:1 unused unused. read = 0000000b. write = don?t care. 0 pswe program store write enable. setting this bit allows writin g a byte of data to the eprom program memory using the movx write instruction. 0: writes to eprom program memory disabled. 1: writes to eprom program memory ena bled; the movx write instruction targets eprom memory. sfr definition 18.2. memkey: eprom memory lock and key bit76543210 name memkey[7:0] type r/w reset 00000000 bit name function 7:0 memkey[7:0] eprom lock and key register. write: this register provides a lock and key fu nction for eprom writ es. eprom writes are enabled by writing 0xa5 fo llowed by 0xf1 to the mem key register. eprom writes are automatically disa bled after the next write is comp lete. if any writes to memkey are performed incorrectly, or if a eprom write operation is attempted while these operations are disabled, th e eprom will be permanently locke d from writes until the next device reset. if an application never wr ites to eprom, it can intentionally lock the eprom by writing a non-0xa5 value to memkey from software. read: when read, bits 1?0 indicate the current eprom lock state. 00: eprom is write locked. 01: the first key code has been written (0xa5). 10: eprom is unlocked (writes allowed). 11: eprom writes disabled until the next reset. c8051t620/621/320/321/322/323 112 rev. 1.1 sfr address = 0xf5 sfr definition 18.3. iapcn: in -application programming control bit76543210 name iapen iapdisd type r/wr/wrrrrrr reset 00000000 bit name function 7 iapen in-application programming enable. 0: in-application programming is disabled. 1: in-application programming is enabled. 6 iaphwd in-application programming hardware disable. this bit disables the in-application programming hardware so the v pp programming pin can be used as a normal gpio pin. note: this bit should not be set less than 1 s after the last eprom write. 0: in-application programming discharge hardware enabled. 1: in-application programming discharge hardware disabled. 5:0 unused unused. read = 000000b. write = don?t care. rev. 1.1 113 c8051t620/621/320/321/322/323 19. power management modes the c8051t620/621/320/321/322/323 devices have three software programmable power management modes: idle, stop, and suspend. idle mode and stop mode are part of the standard 8051 architecture, while suspend mode is an enhanced power-saving mo de implemented by the hi gh-speed oscillator periph- eral. idle mode halts the cpu while leaving the peripherals and clocks active. in stop mode, the cpu is halted, all interrupts and timers (except the missing clock de tector) are inactive, and th e internal oscillator is stopped (analog peripherals remain in their se lected states; the external o scillator is not affected). sus- pend mode is similar to stop mode in that the internal oscillator is halted, but the device can wake on events such as a port mismatch, timer 3 overflow, or activity with the usb transceiver. additionally, the cpu is not halted in suspend mode, so it can run on another oscillator, if desired. since clocks are running in idle mode, power consumption is dependent up on the system clock frequency and the number of peripherals left in active mode before entering idle. stop mode and suspend mode consume the least power because the majority of the device is shut do wn with no clocks active. sfr definition 19.1 describes the power control register (pcon) used to control the c8051t620/621/320/321/322/323's stop and idle power management modes. suspend mode is controlled by the suspend bit in the oscicn register (sfr definition 21.3). although the c8051t620/621/320/321/322/323 has idle, stop, and suspend modes available, more control over the device power can be achieved by enabling/di sabling individual peripherals as needed. each ana- log peripheral can be disabled when not in use and pl aced in low power mode. digital peripherals, such as timers or serial buses, draw little power when they ar e not in use. turning off oscillators lowers power con- sumption considerably, at the expense of reduced functionality. 19.1. idle mode setting the idle mode select bit (pcon.0) causes the hardware to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes execution. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle mode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pen ding interrupt will be serviced and the next in struction to be executed after the return from interrupt (reti) will be the instruction immedi ately following the one that se t the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. note: if the instructio n following the write of the idle bit is a sing le-byte instruction and an interrupt occurs during the execution phase of the instruction that sets the idle bit, the cpu may not wake from idle mode when a future interrupt occurs. therefore, instructi ons that set the idle bit should be followed by an instruction that has two or mo re opcode bytes, for example: // in ?c?: pcon |= 0x01; // set idle bit pcon = pcon; // ... followed by a 3-cycle dummy instruction ; in assembly: orl pcon, #01h ; set idle bit mov pcon, pcon ; ... followed by a 3-cycle dummy instruction if enabled, the watchdog timer (wdt) will eventually cause an internal watchdog reset a nd thereby termi- nate the idle mode. this feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the pcon register. if this behavior is not desired, th e wdt may be disabled by software prior to entering the idle mo de if the wdt was initially configured to allow this operation. this pro- c8051t620/621/320/321/322/323 114 rev. 1.1 vides the opportunity for additional power savings, allo wing the system to remain in the idle mode indefi- nitely, waiting for an external stimul us to wake up the system. refer to section ?20.6. pca watchdog timer reset? on page 120 for more information on the use a nd configuration of the wdt. 19.2. stop mode setting the stop mode select bit (pco n.1) causes the controller core to enter stop mode as soon as the instruction that sets the bit complete s execution. in stop mode the intern al oscillator, cpu, and all digital peripherals are stopp ed; the state of the external oscillator circ uit is not affected. ea ch analog peripheral (including the external oscillator circ uit) may be shut down individually prior to entering stop mode. stop mode can only be terminated by an internal or external reset. on reset, the device performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detector will cause an inte rnal reset and thereby te rminate the stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout. by default, when in stop mode the internal regulator is still active. ho wever, the regulator can be config- ured to shut down while in stop mode to save pow er. to shut down the regulator in stop mode, the stopcf bit in register reg01cn should be set to 1 prior to setting the stop bit (see sfr definition 11.1). if the regulator is shut down using the stopcf bit, only the rst pin or a full power cycle are capa- ble of resetting the device. 19.3. suspend mode setting the suspend bit (oscicn.5) causes the hardwa re to halt the high-frequency in ternal oscillator and go into suspend mode as soon as the instruction t hat sets the bit completes execution. all internal reg- isters and memory maintain their or iginal data. the cpu is not halted in suspend, so code can still be exe- cuted using an oscillator other than the internal high frequency oscillator. most digital peripherals are not active in suspend mode. the exception to this are th e usb0 transceiver, port match feature, and timer 3, when it is run from an extern al oscillator source or the in ternal low-frequency oscillator. suspend mode can be terminated by four types of events: a port match (described in section ?22.5. port match? on page 144), a timer 3 overflow (described in section ?28.3. timer 3? on page 256), resume sig- nalling on the usb data pins, or a device reset event. note that in order to ru n timer 3 in suspend mode, the timer must be configured to clock from either th e external clock source or the internal low-frequency oscillator source. when suspend mode is terminated, the de vice will continue execut ion on the instruction following the one that set the suspend bit. if the wake event (usb0 resume sign alling, port match, or timer 3 overflow) was configured to generate an interrupt, t he interrupt will be serv iced upon waking the device. if suspend mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. rev. 1.1 115 c8051t620/621/320/321/322/323 sfr address = 0x87 sfr definition 19.1. pcon: power control bit76543210 name gf[5:0] stop idle type r/w r/w r/w reset 00000000 bit name function 7:2 gf[5:0] general purpose flags 5?0. these are general purpose flags for use under software control. 1stop stop mode select. setting this bit will place the cip-51 in stop mode. this bit will always be read as 0. 1: cpu goes into stop mode (i nternal oscillator stopped). 0idle idle: idle mode select. setting this bit will place the cip-51 in idle mode. this bit will always be read as 0. 1: cpu goes into idle mode. (shuts off clo ck to cpu, but clock to timers, interrupts, serial ports, and analog peripherals are still active.) c8051t620/621/320/321/322/323 116 rev. 1.1 20. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. on entry to this reset state, th e following occur: ? cip-51 halts program execution ? special function registers (sfrs) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal data memory are unaffected during a reset; any prev iously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effectively lo st, even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones) in open-drain mode. weak pullups are enabled dur- ing and after the reset. for v dd monitor and power-on resets, the rst pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to the inter- nal oscillator. the watchdog timer is enabled with the system clock divided by 12 as its clock source. pro- gram execution begins at location 0x0000. figure 20.1. reset sources pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel px.x px.x en swrsf internal oscillator system clock cip-51 microcontroller core extended interrupt handler clock select en wdt enable mcd enable extclk external oscillator drive errant otp operation rst (wired-or) power on reset '0' + - comparator 0 c0rsef vdd + - supply monitor enable low frequency oscillator rev. 1.1 117 c8051t620/621/320/321/322/323 20.1. power-on reset during power-up, the device is held in a reset state and the rst pin is driven low until v dd settles above v rst . a delay occurs before the device is released from reset; the delay decreases as the v dd ramp time increases (v dd ramp time is defined as how fast v dd ramps from 0 v to v rst ). figure 20.2. plots the power-on and v dd monitor event timing. the maximum v dd ramp time is 1 ms; slower ramp times may cause the device to be released from reset before v dd reaches the v rst level. for ramp times less than 1 ms, the power-on reset delay (t pordelay ) is typically less than 0.3 ms. on exit from a power-on or v dd monitor reset, the porsf flag (rstsrc. 1) is set by hardware to logic 1. when porsf is set, all of the othe r reset flags in the rstsrc regist er are indeterminate (porsf is cleared by all other resets). since all resets caus e program execution to begin at the same location (0x0000) software can read the porsf flag to determine if a power-up was the cause of reset. the con- tent of internal data memory should be assumed to be undefined after a power-on reset. the v dd monitor is enabled following a power-on reset. figure 20.2. power-on and v dd monitor reset timing 20.2. power-fail reset / v dd monitor when a power-down transition or power irregularity causes v dd to drop below v rst , the power supply monitor will drive the rst pin low and hold the cip-51 in a reset state (see figure 20.2). when v dd returns to a level above v rst , the cip-51 will be released from the reset state. note that even though internal data memory contents are not altered by the power-fa il reset, it is impossib le to determine if v dd dropped below power-on reset vdd monitor reset rst t supply voltage logic high logic low t pordelay v d d v rst vdd c8051t620/621/320/321/322/323 118 rev. 1.1 the level required for data retenti on. if the porsf flag reads 1, the data may no longer be valid. the v dd monitor is enabled after power-on resets. its defined state (enabled/disabled) is not altered by any other reset source. for example, if the v dd monitor is disabled by code and a software reset is performed, the v dd monitor will still be disabled after the reset. i mportant note: if the v dd monitor is being turned on from a disabled state, it should be enabled before it is selected as a reset source. selecting the v dd monitor as a reset source before it is enabled and stabi- lized may cause a system reset. in some applications, this reset may be undesirable. if this is not desirable in the application, a delay should be introduced betwe en enabling the monitor and selecting it as a reset source. the procedure for enabling the v dd monitor and configuring it as a reset source from a disabled state is shown below: 1. enable the v dd monitor (vdmen bit in vdm0cn = 1). 2. if necessary, wait for the v dd monitor to stabilize (see table 7.4 for the v dd monitor turn-on time). 3. select the v dd monitor as a reset source (porsf bit in rstsrc = 1). see figure 20.2 for v dd monitor timing; note that the power-on -reset delay is not incurred after a v dd monitor reset. see table 7.4 for complete electrical characteristics of the v dd monitor. rev. 1.1 119 c8051t620/621/320/321/322/323 sfr address = 0xff 20.3. external reset the external rst pin provides a means for external circuitry to force the device into a reset state. assert- ing an active-low signal on the rst pin generates a reset; an external pullup and/or decoupling of the rst pin may be necessary to avoid erroneous noise- induced resets. see table 7.4 for complete rst pin spec- ifications. the pinrsf flag (rstsrc.0) is set on exit from an external reset. 20.4. missing cl ock detector reset the missing clock detector (mcd) is a one-shot circuit that is triggered by the syst em clock. if the system clock remains high or low for more than the mcd time-out, a reset will be generated. after a mcd reset, the mcdrsf flag (rstsrc.2) will read 1, signifying the mcd as the reset source; otherwise, this bit reads 0. writing a 1 to the mcdrsf bit enables the missing clock detector; writing a 0 disables it. the state of the rst pin is unaffected by this reset. 20.5. comparator0 reset comparator0 can be configured as a reset source by writing a 1 to the c0rsef flag (rstsrc.5). comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted rese t. the comparator0 reset is active-low: if the non- inverting input voltage (on cp0+) is le ss than the inverting input voltage (on cp0-), the device is put into the reset state. after a compar ator0 reset, the c0rsef flag (rst src.5) will read 1 signifying comparator0 as the reset source; otherwise, this bit reads 0. the state of the rst pin is unaffected by this reset. sfr definition 20.1. vdm0cn: v dd monitor control bit7654321 0 name vdmen vddstat type r/wrrrrrr r reset varies varies varies varies varies varies varies varies bit name function 7vdmen v dd monitor enable. this bit turns the v dd monitor circuit on/off. the v dd monitor cannot generate sys- tem resets until it is also selected as a reset source in register rstsrc (sfr def- inition 20.2). selecting the v dd monitor as a reset source before it has stabilized may generate a system reset. in systems wher e this reset would be undesirable, a delay should be introduced between enabling the v dd monitor and selecting it as a reset source. see table 7.4 for the minimum v dd monitor turn-on time. 0: v dd monitor disabled. 1: v dd monitor enabled. 6vddstat v dd status. this bit indicates the current power supply status (v dd monitor output). 0: v dd is at or below the v dd monitor threshold. 1: v dd is above the v dd monitor threshold. 5:0 unused unused. read = varies; write = don?t care. c8051t620/621/320/321/322/323 120 rev. 1.1 20.6. pca watchdog timer reset the programmable watchdog timer (wdt) function of the programmable counter array (pca) can be used to prevent software from running out of cont rol during a system malfunction. the pca wdt function can be enabled or disabled by software as desc ribed in section ?29.4. watchdog timer mode? on page 273; the wdt is enabled and clocked by sysclk / 12 following any reset. if a system malfunction prevents user software from updating the wdt, a re set is generated and the wdtrsf bit (rstsrc.5) is set to 1. the state of the rst pin is unaffected by this reset. 20.7. eprom error reset if an eprom program read or write targets an illegal address, a system reset is generated . this may occur due to any of the following: ? programming hardware attempts to write or read an eprom location which is above the user code space address limit. ? an eprom read from firmware is attempted above user code space. this occurs when a movc operation is attempted above the user code space address limit. ? a program read is attempted above user code space. this occurs when user code attempts to branch to an address above the user code space address limit. the memerr bit (rstsrc.6) is set following an eprom error reset. the state of the rst pin is unaf- fected by this reset. 20.8. software reset software may force a reset by wr iting a 1 to the swrsf bit (rstsr c.4). the swrsf bit will read 1 fol- lowing a software forced reset. the state of the rst pin is unaffected by this reset. 20.9. usb reset writing 1 to the usbrsf bit in register rstsrc select s usb0 as a reset source. with usb0 selected as a reset source, a system reset will be gener ated when either of the following occur: 1. reset signaling is detected on the usb network. the usb func tion controller (usb0) must be enabled for reset signaling to be detected. see section ?2 3. universal serial bus controller (usb0)? on page 155 for information on the usb function controller. 2. a falling or rising voltage on the vbus pin matches the edge polarity select ed by the vbpol bit in register reg01cn. see section ?11. voltage regulators (reg0 and reg1)? on page 59 for details on the vbus detection circuit. the usbrsf bit will read 1 following a usb reset. the st ate of the /rst pin is unaffected by this reset. rev. 1.1 121 c8051t620/621/320/321/322/323 sfr address = 0xef sfr definition 20.2. rstsrc: reset source bit76543210 name usbrsf memerr c0rsef swrsf wdtrsf mcdrsf porsf pinrsf type r/w r r/w r/w r r/w r/w r reset varies varies varies varies varies varies varies varies bit name description write read 7 usbrsf usb reset flag writing a 1 enables usb as a reset source. set to 1 if usb caused the last reset. 6 memerr eprom error reset flag. n/a set to 1 if eprom read/write error caused the last reset. 5 c0rsef comparator0 reset enable and flag. writing a 1 enables comparator0 as a reset source (active-low). set to 1 if comparator0 caused the last reset. 4swrsf software reset force and flag. writing a 1 forces a sys- tem reset. set to 1 if last reset was caused by a write to swrsf. 3 wdtrsf watchdog timer reset flag. n/a set to 1 if watchdog timer overflow caused the last reset. 2 mcdrsf missing clock detector enable and flag. writing a 1 enables the missing clock detector. the mcd triggers a reset if a missing clock condition is detected. set to 1 if missing clock detector timeout caused the last reset. 1porsf power-on / v dd monitor reset flag, and v dd monitor reset enable. writing a 1 enables the v dd monitor as a reset source. writing 1 to this bit before the v dd monitor is enabled and stabilized may cause a system reset. set to 1 anytime a power- on or v dd monitor reset occurs. when set to 1 all other rstsrc flags are inde- terminate. 0pinrsf hw pin reset flag. n/a set to 1 if rst pin caused the last reset. note: do not use read-modify-write operations on this register c8051t620/621/320/321/322/323 122 rev. 1.1 21. oscillators and clock selection c8051t620/621/3 20/321/322/323 devices include a progra mmable internal high-f requency oscillator, a programmable internal low-fr equency oscillator, and an external oscillator drive ci rcuit. the internal high- frequency oscillator can be enabled/disabled and calibrated using the oscicn and oscicl registers, as shown in figure 21.1. the internal low-frequency oscillato r can be enabled/disabl ed and calibra ted using the osclcn register. the sys tem clock can be sourced by the external oscillator ci rcuit or either internal oscillator. both internal oscillators offer a selectable post-scalin g feature. the usb clock (usbclk) can be derived from the internal oscilla tors or external oscillator. figure 21.1. oscillator options osc programmable internal clock generator input circuit en sysclk oscicl oscicn ioscen ifrdy suspend ifcn1 ifcn0 oscxcn xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 clksel usbclk2 usbclk1 usbclk0 clksl2 clksl1 clksl0 osclcn osclen osclrdy osclf3 osclf2 osclf1 osclf0 oscld1 oscld0 low frequency oscillator en n osclf osclf oscld usbclk clkmul mulen mulint mulrdy mulsel1 mulsel0 usbclk2-0 internal hfo / 8 exosc exosc / 2 exosc / 3 exosc / 4 internal lfo internal hfo n 4 2 oscld xtal1 xtal2 rc mode vdd xtal2 option 1 10m ? c mode xtal2 cmos mode xtal2 rev. 1.1 123 c8051t620/621/320/321/322/323 21.1. system clock selection the clksl[2:0] bits in register cl ksel select which osc illator source is used as the system clock. clksl[2:0] must be set to 001b for t he system clock to run from the exte rnal oscillator; however the exter- nal oscillator may still clock certain per ipherals (timers, pca) when the inte rnal oscillator is selected as the system clock. the system clock may be switched on-the -fly between the internal oscillators and external oscillator so long as the selected clock source is en abled and running. the internal high-frequency and low-frequency oscillators require little start-up ti me and may be selected as the system clock immediately fo llowing the register writ e which enables the oscillator. the external rc and c modes also typically require no startup time. 21.2. usb clock selection the usbclk[2:0] bits in register clksel select which oscillator source is used as the usb clock. the usb clock may be derived from the internal oscillators, a divided vers ion of the intern al high-frequency oscillator, or a divided version of the external osc illator. note that the usb clock must be 48 mhz when operating usb0 as a full speed function; the usb cl ock must be 6 mhz when operating usb0 as a low speed function. see sfr definition 21 .1 for usb clock selection options. some example usb clock configurations for full and low speed mode are given below: usb full speed (48 mhz) internal oscillator clock signal input source selection register bit settings usb clock internal oscillator* usbclk = 000b internal oscillator divide by 1 ifcn = 11b external oscillator clock signal input source selection register bit settings usb clock external oscillator usbclk = 010b external oscillator cmos oscillator mode 48 mhz oscillator xoscmd = 010b note: clock recovery must be enabled for this configuration. usb low speed (6 mhz) internal oscillator clock signal input source selection register bit settings usb clock internal oscillator / 8 usbclk = 001b internal oscillator divide by 1 ifcn = 11b external oscillator clock signal input source selection register bit settings usb clock external oscillator / 4 usbclk = 101b external oscillator cmos oscillator mode 24 mhz oscillator xoscmd = 010b crystal oscillator mode 24 mhz oscillator xoscmd = 110b xfcn = 111b c8051t620/621/320/321/322/323 124 rev. 1.1 sfr address = 0xa9 sfr definition 21.1. clksel: clock select bit76543210 name usbclk[2:0] outclk clksl[2:0] type r r/w r/w r/w reset 00000000 bit name function 7 unused unused. read = 0b; write = don?t care 6:4 usbclk[2:0] usb clock source select bits. 000: usbclk derived from the in ternal high-frequency oscillator. 001: usbclk derived from the inte rnal high-frequency oscillator / 8. 010: usbclk derived from the external oscillator. 011: usbclk derived from th e external oscillator / 2. 100: usbclk derived from the external oscillator / 3. 101: usbclk derived from the external oscillator / 4. 110: usbclk derived from the in ternal low-frequency oscillator. 111: reserved. 3 outclk crossbar clock out select. if the sysclk signal is enabled on the crossbar, this bit selects between outputting sysclk and sysclk synchronized with the port i/o pins. 0: enabling the crossbar sysclk signal outputs sysclk. 1: enabling the crossbar sysclk signal outputs sysclk synchronized with the port i/o. 2:0 clksl[2:0] system clock source select bits. 000: sysclk derived from th e internal high-fr equency oscillator and scaled per the ifcn bits in register oscicn. 001: sysclk derived from the external oscillator circuit. 010: sysclk derived from the internal high-frequency oscillator / 2. 011: sysclk derived from the internal high-frequency oscillator. 100: sysclk derived from th e internal low- frequency oscillato r and scaled per the oscld bits in register osclcn. 101-111: reserved. rev. 1.1 125 c8051t620/621/320/321/322/323 21.3. programmable internal high-frequency (h-f) oscillator all c8051t620/621/3 20/321/322/323 devices include a programmable in ternal high-frequency oscillator that defaults as the system clock af ter a system reset. the in ternal oscillator period can be adjusted via the oscicl register as defined by sfr definition 21.2. on c8051t620/621/320/321/322/323 de vices, oscicl is factory calibra ted to obtain a 48 mhz base fre- quency. note that the system clock ma y be derived from the programmed inte rnal oscillator divided by 1, 2, 4, or 8 after a divide by 4 stage, as defined by the ifcn bits in register oscicn. the divide value defaults to 8 following a reset, which results in a 1.5 mhz system clock. 21.3.1. internal os cillator suspend mode when software writes a logic 1 to suspend (oscicn.5) , the internal oscillator is suspended. if the sys- tem clock is derived from t he internal oscillator, the input clock to the peripheral or cip-51 will be stopped until one of the following events occur: ? port 0 match event. ? port 1 match event. ? timer3 overflow event. ? usb0 transceiver resume signalling when one of the oscillator awakening events occur, the internal oscillato r, cip-51, and affe cted peripherals resume normal operation, regardless of whether the event also causes an interrupt. the cpu resumes execution at the instruction foll owing the write to the suspend bit. note: the prefetch engine can be turned off in suspend mode to save power. additionally, both voltage regulators (reg0 and reg1) have low-power modes for additional power savings in suspend mode. see section ?13. prefetch engine? on page 74 and section ?11. voltage regulators (reg0 and reg1)? on page 59 for more information. sfr address = 0xb3 sfr definition 21.2. oscicl: intern al h-f oscillator calibration bit76543210 name oscicl[6:0] type rr/w reset 0 varies varies varies var ies varies varies varies bit name function 7 unused unused . read = 0; write = don?t care 6:0 oscicl[6:0] internal oscillator calibration bits. these bits determine the internal oscillato r period. when set to 0000000b, the h-f oscillator operates at its fa stest setting. when set to 111 1111b, the h-f oscillator operates at its slowest setting. the reset value is factory calibrated to generate an internal oscillator frequency of 48 mhz. c8051t620/621/320/321/322/323 126 rev. 1.1 sfr address = 0xb2 sfr definition 21.3. oscicn: inte rnal h-f oscillator control bit76 5 43210 name ioscen ifrdy suspend ifcn[1:0] type r/w r r/w r r r r/w reset 11 0 00000 bit name function 7ioscen internal h-f oscillator enable bit. 0: internal h-f oscillator disabled. 1: internal h-f oscillator enabled. 6ifrdy internal h-f oscillator frequency ready flag. 0: internal h-f oscillator is no t running at pr ogrammed frequency. 1: internal h-f oscillator is running at progr ammed frequency. 5 suspend internal oscillator suspend enable bit. setting this bit to logic 1 places the in ternal oscillator in suspend mode. the inter- nal oscillator resumes operation when one of the suspend mode awakening events occurs. 4:2 unused unused . read = 000b; write = don?t care 1:0 ifcn[1:0] internal h-f oscillator fre quency divider control bits. the internal h-f oscillator is divided by the ifcn bit setting after a divide-by-4 stage. 00: sysclk can be derived from internal h-f oscillator divided by 8 (1.5 mhz). 01: sysclk can be derived from internal h-f oscillator divided by 4 (3 mhz). 10: sysclk can be derived from internal h-f oscillator divided by 2 (6 mhz). 11: sysclk can be derived from internal h-f oscillator divid ed by 1 (12 mhz). rev. 1.1 127 c8051t620/621/320/321/322/323 21.4. clock multiplier the c8051t620/621/320/321/3 22/323 device includes a 48 mhz high-frequency oscillator instead of a 12 mhz oscillator and a 4x clock multiplier, so the usb0 module can be run direct ly from the internal high- frequency oscillator. for compatibilit y with the flash development platform , however, the clkmul register (sfr definition 21.4) behaves as if the clock multiplier is present. sfr address = 0xb9 sfr definition 21.4. clkmul: clock multiplier control bit76543210 name mulen mulinit mulrdy mulsel[1:0] type rrrrrr r reset 11100000 bit name description write read 7mulen clock multiplier enable bit. 0: clock multiplier disabled. 1: clock multiplier enabled. this bit always reads 1. 6mulinit clock multiplier initialize bit. this bit should be a 0 when the clock multiplier is enabled. once enabled, writing a 1 to this bit will initialize the clock multiplier. the mulrdy bit reads 1 when the clock multiplier is stabilized. this bit always reads 1. 5 mulrdy clock multiplier ready bit. 0: clock multiplier not ready. 1: clock multiplier ready (locked). this bit always reads 1. 4:2 unused unused . read = 000b; write = don?t care 1:0 mulsel[1:0] clock multiplier input select bits. these bits select the clock supplied to the clock multiplier. 00: internal high-f requency oscillator 01: external oscillator 10: external oscillator/2 11: reserved. these bits always read 00. c8051t620/621/320/321/322/323 128 rev. 1.1 21.5. programmable internal low-frequency (l-f) oscillator all c8051t620/621/32 0/321/322/323 devices include a programmable low- frequency internal oscillator, which is calibrated to a nominal frequ ency of 80 khz. the low-frequency oscillator circuit includes a divider that can be changed to divide the clock by 1, 2, 4, or 8, using the oscld bits in the osclcn register (see sfr definition 21.5). additionally, the osclf[3:0] bi ts can be used to adjust the oscillator?s output fre- quency. 21.5.1. calibrating the internal l-f oscillator timers 2 and 3 include capture func tions that can be used to capture the oscillato r frequency, when run- ning from a known time base. when either timer 2 or timer 3 is co nfigured for l-f oscillator capture mode, a falling edge (tim er 2) or rising edge (tim er 3) of the low-frequency oscillator?s output will cause a capture event on the corresponding timer. as a capture event occurs, the current timer value (tmrnh:tmrnl) is copied into the timer reload regi sters (tmrnrlh:tmrnrll). by recording the differ- ence between two successive time r capture values, the lo w-frequency oscillator? s period can be calcu- lated. the osclf bits can then be adjusted to produce the desire d oscillator frequency. sfr address = 0x86 sfr definition 21.5. osclcn: inte rnal l-f oscill ator control bit76543210 name osclen osclrdy oscl f[3:0] oscld[1:0] type r/w r r.w r/w reset 0 0 varies varies varies varies 0 0 bit name function 7osclen internal l-f oscillator enable. 0: internal l-f oscillator disabled. 1: internal l-f oscillator enabled. 6osclrdy internal l-f oscillator ready. 0: internal l-f oscillator frequency not stabilized. 1: internal l-f oscilla tor frequency stabilized. note: osclrdy is only set back to 0 in the event of a device reset or a change to the oscld[1:0] bits. 5:2 osclf[3:0] internal l-f oscillator frequency control bits. fine-tune control bits for the internal l-f oscillator fr equency. when set to 0000b, the l-f oscillator oper ates at its fastest setting. when set to 1111b, the l-f oscillator operates at its slowest setting. 1:0 oscld[1:0] internal l-f oscillator divider select. 00: divide by 8 selected. 01: divide by 4 selected. 10: divide by 2 selected. 11: divide by 1 selected. rev. 1.1 129 c8051t620/621/320/321/322/323 21.6. external osci llator drive circuit the external oscillator circuit may drive an external cr ystal, ceramic resona tor, capacitor, or rc network. a cmos clock may also provide a clock input. figure 21.1 shows a block diagram of the four external oscil- lator options. the external oscillator is enabled a nd configured using the oscxcn register (see sfr defi- nition 21.6). important note on external oscillator usage: port pins must be configured when using the external oscillator circuit. when the external oscillator drive ci rcuit is enabled in crystal/resonator mode, port pins p0.2 and p0.3 are used as xtal1 and xtal2, respectively. when th e external oscillator drive circuit is enabled in capacitor, rc, or cmos clock mode, port pin p0.3 is used as xtal2. the port i/o crossbar should be configured to sk ip the port pin used by the oscillator circ uit; see section ?22.3. priority crossbar decoder? on page 137 for crossbar co nfiguration. additionally, when using the external oscillator circuit in crystal/resonator, capacitor, or rc mode, the associated port pins should be configured as analog inputs . in cmos clock mode, the associated pin should be configured as a digital input . see section ?22.4. port i/o initialization? on page 141 for de tails on port inpu t mode selection. the external oscillato r output may be selected as the system clock or used to clock some of the digital peripherals (e.g. timers, pca, etc.). see the data shee t chapters for each digital peripheral for details. see section ?7. electrical characteristics? on p age 33 for complete o scillator specifications. 21.6.1. external crystal mode if a crystal or ceramic resonator is used as the ex ternal oscillator, the crys tal/resonator and a 10 m ?? resis- tor must be wired across the xtal1 and xtal2 pins as shown in figure 21.1, ?crystal mode?. appropriate loading capacitors should be added to xtal1 and xtal2, and both pins should be configured for analog i/o with the digital output drivers disabled. the capacitors shown in the external crystal configur ation provide the load capacitance required by the crystal for correct oscillation. these capacitors are ?in series? as seen by the crystal and ?in parallel? with the stray capacitance of the xtal1 and xtal2 pins. note: the recommended load capacitance depends upon the crystal and the manufacturer. please refer to the crystal data sheet when completing these calculations. the equation for determining the load capacitance for two capacitors is where: c a and c b are the capacitors connec ted to the crystal leads. c s is the total stray capacitance of the pcb. the stray capacitance for a typical layout where the crysta l is as close as possible to the pins is 2-5 pf per pin. if c a and c b are the same (c), then the equation becomes for example, a tuning-fork crystal of 32 khz with a recommended load capacitance of 12.5 pf should use the configuration shown in figure 21.1 , option 1. with a stray capacitance of 3 pf per pin (6 pf total), the 13 pf capacitors yield an equivalent capacitance of 12.5 pf across the crystal, as shown in figure 21.2. c l c a c b ? c a c b + -------------------- c s + = c l c 2 --- - c s += c8051t620/621/320/321/322/323 130 rev. 1.1 figure 21.2. external crystal example important note on external crystals: crystal oscillator circuits are qui te sensitive to pcb layout. the crystal should be placed as close as possible to the xtal pins on the device. the traces should be as short as possible and shielded with ground plane fr om any other traces which could introduce noise or interference. when using an external crystal, the external oscillator drive circuit must be configured by software for crys- tal oscillator mode or crystal oscillator mode with divide by 2 stage . the divide by 2 stage ensures that the clock derived from the external o scillator has a duty cycle of 50%. t he external oscillator frequency con- trol value (xfcn) must also be specified based on the crystal frequency (see sfr definition 21.6). when the crystal oscillator is first enabled, the external osc illator valid detector allo ws software to deter- mine when the external system clock is valid and running. sw itching to the external oscilla tor before the crystal oscillator has stabilized can re sult in unpredictable behavior. th e recommended procedure for start- ing the crystal is: 1. configure xtal1 and xtal2 for analog i/o. 2. disable the xtal1 and xtal2 digital output drivers by writing 1s to the appropriate bits in the port latch register. 3. configure and enable the external oscillator. 4. wait at least 1 ms. 5. poll for xtlvld => '1'. 6. switch the system clock to the external oscillator. 13 pf 13 pf 32 khz xtal1 xtal2 10 m ? rev. 1.1 131 c8051t620/621/320/321/322/323 21.6.2. external rc example if an rc network is used as an external oscillator so urce for the mcu, the circ uit should be configured as shown in figure 21.1, ?rc mode?. the capacitor should be no greater than 100 pf; however, for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to deter- mine the required external oscilla tor frequency control va lue (xfcn) in the oscxcn register, first select the rc network value to prod uce the desired frequency of oscilla tion, according to equation , where f = the frequency of oscillation in mh z, c = the capacitor value in pf, an d r = the pull-up resistor value in k? . equation 21.1. rc mode oscillator frequency for example: if the frequency desired is 100 khz, let r = 246 k ? and c = 50 pf: f = 1.23( 10 3 ) / rc = 1.23 ( 10 3 ) / [ 246 x 50 ] = 0.1 mhz = 100 khz referring to the table in sfr definition 21.6, the required xfcn setting is 010b. 21.6.3. external capacitor example if a capacitor is used as an external oscillator for t he mcu, the circuit should be configured as shown in figure 21.1, ?c mode?. the capacitor should be no greater than 100 pf; however, for very small capaci- tors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to determine the required external oscillato r frequency control value (xfcn) in th e oscxcn register, select the capaci- tor to be used and find the frequen cy of oscillation according to equati on , where f = the frequency of oscil- lation in mhz, c = the ca pacitor value in pf, and v dd = the mcu power supply in volts. equation 21.2. c mode oscillator frequency for example: assume v dd = 3.0 v and f = 150 khz: f = kf / (c x vdd) ? 0.150 mhz = kf / (c x 3.0) since the frequency of roughly 150 khz is desired, sele ct the k factor from the table in sfr definition 21.6 (oscxcn) as kf = 22: 0.150 mhz = 22 / (c x 3.0) ? c x 3.0 = 22 / 0.150 mhz ? c = 146.6 / 3.0 pf = 48.8 pf therefore, the xfcn value to use in this example is 011b and c = 50 pf. f 1.23 10 3 ? rc ? ?? ? = fkf ?? cv dd ? ?? ? = c8051t620/621/320/321/322/323 132 rev. 1.1 sfr address = 0xb1 sfr definition 21.6. oscxcn: ex ternal oscillator control bit76543210 name xclkvld xoscmd[2:0] - xfcn[2:0] type rr / wrr / w reset 00000000 bit name function 7 xclkvld external oscillator valid flag. provides external oscillator status and is valid at all times for all modes of opera- tion except external cmos clock mo de and external cmos clock mode with divide by 2. in these modes, xclkvld always returns 0. 0: external oscillator is unused or not yet stable. 1: external oscillator is running and stable. 6:4 xoscmd[2:0] external oscillat or mode select. 00x: external oscillator circuit off. 010: external cmos clock mode. 011: external cmos clock mode with divide by 2 stage. 100: rc oscillator mode. 101: capacitor oscillator mode. 110: crystal oscillator mode. 111: crystal oscillator mode with divide by 2 stage. 3 unused read = 0; write = don?t care 2:0 xfcn[2:0] external oscillator frequency control bits. set according to the desired frequency for rc mode. set according to the desired k factor for c mode. xfcn crystal mode rc mode c mode 000 f ?? 20 khz f ?? 25 khz k factor = 0.87 001 20 khz ?? f ?? 58 khz 25 khz ?? f ?? 50 khz k factor = 2.6 010 58 khz ?? f ?? 155 khz 50 khz ?? f ?? 100 khz k factor = 7.7 011 155 khz ?? f ?? 415 khz 100 khz ?? f ?? 200 khz k factor = 22 100 415 khz ?? f ?? 1.1 mhz 200 khz ?? f ?? 400 khz k factor = 65 101 1.1 mhz ?? f ?? 3.1 mhz 400 khz ?? f ?? 800 khz k factor = 180 110 3.1 mhz ?? f ?? 8.2 mhz 800 khz ?? f ?? 1.6 mhz k factor = 664 111 8.2 mhz ?? f ?? 25 mhz 1.6 mhz ?? f ?? 3.2 mhz k factor = 1590 rev. 1.1 133 c8051t620/621/320/321/322/323 22. port input/output digital and analog resources are available through 21, 24, or 25 i/o pins, depending on the specific device. port pins p0.0-p2.7 can be defined as general-purpose i/o (gpio), assigned to one of the internal digital resources, or assigned to an analog function as sh own in figure 22.3. port pin p3.0 on can be used as gpio and is shared with the c2 interface data si gnal (c2d). the designer has complete control over which functions are assigned, limited only by the number of physical i/o pins. this resource assignment flexibility is achieved through the use of a priority crossbar decoder. note that the state of a port i/o pin can always be read in the corresponding port latch, regardless of the crossbar settings. the crossbar assigns the selected internal digital resources to the i/o pins based on the priority decoder (figure 22.4). the registers xbr0, xbr1, and xbr2, defined in sfr definition 22.1, sfr definition 22.2, and sfr definition 22.2, are used to select internal digital functions. all port i/os are 5 v tolerant (refer to figure 22.2 for the port cell circuit). the port i/o cells are configured as either push-pull or open-drain in the port output mode registers (pnmdout, where n = 0,1). complete electrical specifications for port i/o are given in table 7.3 on page 35. figure 22.1. port i/o functional block diagram p2 i/o cells xbr0, xbr1, xbr2, pnskip registers digital crossbar priority decoder p0 i/o cells p0.0 p0.7 8 port match p0mask, p0mat p1mask, p1mat p1 i/o cells p1.0 8 (port latches) p0 (p0.0-p0.7) (p1.0-p1.7) 8 8 p1 p3 i/o cell p3 (p3.0) 1 pnmdout, pnmdin registers p1.7 p3.0 to analog peripherals (adc0, cp0, cp1, vref, extclk) external interrupts ex0 and ex1 (p2.0-p2.6) 7 p2 p2.0 7 p2.7 2 uart0 (internal digital signals) highest priority lowest priority sysclk 2 smbus t0, t1 2 6 pca 4 spi cp0 outputs 2 2 uart1 cp1 outputs 2 c8051t620/621/320/321/322/323 134 rev. 1.1 22.1. port i/o m odes of operation port pins use the port i/o cell shown in figure 22.2. each port i/o cell can be configured by software for analog i/o or digital i/o using the pnmdin registers. on reset, all port i/o cells default to a high impedance state with weak pull-ups enabled until the crossbar is enabled (xbare = 1). 22.1.1. port pins conf igured for analog i/o any pins to be used as comparator or adc input, external oscillator inpu t/output, or vref should be con- figured for analog i/o (pnmdin.n = 1). when a pin is configured for analog i/o, its weak pullup, digital driver, and digital receiver are disabled. port pins configured for analog i/o will al ways read back a value of 0. configuring pins as analog i/o saves power and isolates the port pin from digital interference. port pins configured as digital inputs may still be used by analog peripherals; howe ver, this practice is not recom- mended and may result in measurement errors. 22.1.2. port pins configured for digital i/o any pins to be used by digital peripherals (uart, sp i, smbus, etc.), external digital event capture func- tions, or as gpio should be configured as digital i/o (pnmdin.n = 1). for digital i/o pins, one of two output modes (push-pull or open-drain) must be selected using the pnmdout registers. push-pull outputs (pnmdout.n = 1) drive the port pad to the v io or gnd supply rails based on the output logic value of the port pin. open-drain outputs have the high side driver disabled; therefore, they only drive the port pad to gnd when the output logic value is 0 and become high impedance inputs (both high and low drivers turned off) when the output logic value is 1. when a digital i/o cell is placed in the high impedance st ate, a weak pull-up transistor pulls the port pad to the v dd supply voltage to ensure the digital input is at a defined logic state. weak pull-ups are disabled when the i/o cell is driven to gnd to minimize power consumption and may be globally disabled by setting weakpud to 1. the user should ensure that digital i/o ar e always internally or ex ternally pulled or driven to a valid logic state to minimize power consumption. port pins configured for digital i/o always read back the logic state of the port pad, regardless of the output logic value of the port pin. figure 22.2. port i/o cell block diagram gnd vio vio (weak) port pad to/from analog peripheral pxmdin.x (1 for digital) (0 for analog) px.x ? output logic value (port latch or crossbar) xbare (crossbar enable) px.x ? input logic value (reads 0 when pin is configured as an analog i/o) pxmdout.x (1 for push-pull) (0 for open-drain) weakpud (weak pull-up disable) rev. 1.1 135 c8051t620/621/320/321/322/323 22.1.3. interfacing po rt i/o to 5v logic all port i/o configured for digital, open-drain operation are capable of interfacing to digital logic operating at a supply voltage higher than v io and less than 5.25v. an external pull-up resistor to the higher supply volt- age is typically required for most systems. important note: in a multi-voltage interface, the external pull-up resistor should be sized to allow a current of at least 150ua to flow into the port pin when the supply voltage is between (v io + 0.6v) and (v io + 1.0v). once the port pin voltage increases beyond this range, the current flowing into the port pin is mini- mal. 22.2. assigning port i/o pins to analog and digital functions port i/o pins can be assigned to various analog, digita l, and external interrupt functions. the port pins assigned to analog functions should be configured for ana log i/o, and port pins assi gned to digital or exter- nal interrupt functions should be configured for digital i/o. 22.2.1. assigning port i/o pins to analog functions table 22.1 shows all available analog func tions that require port i/o assignments. port pins selected for these analog functions should have their corresponding bit in pnskip set to 1. this reserves the pin for use by the analog function and do es not allow it to be claimed by the crossbar. table 22.1 shows the potential mapping of port i/o to each analog function. 22.2.2. assigning port i/o pins to digital functions any port pins not assigned to analog functions may be assigned to digital functi ons or used as gpio. most digital functions rely on the crossbar for pin assi gnment; however, some digital functions bypass the crossbar in a manner similar to the analog functions listed above. port pins used by these digital func- tions and any port pins selected for use as gpio should have their corresponding bit in pnskip set to 1. table 22.2 shows all available digital functions and the potential mapping of port i/o to each digital function. table 22.1. port i/o assignment for analog functions analog function potentially assignable port pins suffers) used for assignment adc input p0.0, p0 .1, p0.4, p0.5, p1.0- p3.0 amx0p, pnskip comparator input p0.0, p0.1, p0.4, p0.5, p1.0-p1.7, p2.0-p2.5 cpt0mx, cpt1mx, pnskip voltage reference (vref0) p0.7 ref0cn, pnskip external oscillator in crystal mode (xtal1, xtal2) p0.2, p0.3 oscxcn, pnskip external oscillator in rc or c mode (xtal2) p0.3 oscxcn, pnskip c8051t620/621/320/321/322/323 136 rev. 1.1 22.2.3. assigning port i/o pins to external digital event capture functions external digital event captur e functions can be used to trigger an interrupt or wake the device from a low power mode when a transition occurs on a digital i/o pin. the digital event capture functions do not require dedicated pins and will function on both gpio pins (pnskip = 1) and pi ns in use by the crossbar (pnskip = 0). external digital event capture functions cannot be used on pins configured for analog i/o. table 22.3 shows all available external digital event capture functions. table 22.2. port i/o assignment for digital functions digital function potentially assignable port pins suffers) used for assignment uart0, spi0, smbus, cp0, cp0a, cp1, cp1a, sysclk, pca0 (cex0-4 and eci), t0, t1, or uart1. any port pin available for assignment by the crossbar. this includes p0.0 - p2.6 pins which have their pnskip bit set to 0. note: the crossbar will always assign uart0 pins to p0.4 and p0.5. xbr0, xbr1, xbr2 any pin used for gpio p0.0 - p3.0 pnskip rev. 1.1 137 c8051t620/621/320/321/322/323 22.3. priority crossbar decoder the priority crossbar decoder assigns a priority to each i/o function, starting at the top with uart0. when a digital resource is selected, the l east-significant unassigned port pin is assigned to that resource (exclud- ing uart0, which is always at pins 4 and 5). if a port pin is assigned, the crossbar skips that pin when assigning the next selected resource. additionally, the crossbar will skip port pins whose associated bits in the pnskip registers are set. the pnskip registers allow so ftware to skip port pins that are to be used for analog input, dedicate d functions, or gpio. because of the nature of the priority crossbar decoder, not all peripherals can be located on all port pins. figure 22.3 shows the possible pins on which peripheral i/o can appear. important note on crossbar configuration: if a port pin is claimed by a peripheral without use of the crossbar, its corresponding pnskip bit should be set. the crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. registers xbr0, xbr1, and xbr2 are used to assign the digital i/o resources to the physical i/o port pins. note that when the smbus is selected, the cr ossbar assigns both pins associated with the smbus (sda and scl); when a uart is selected, the cross bar assigns both pins associated with the uart (tx and rx). uart0 pin assignments are fixed for bootlo ading purposes: uart tx0 is always assigned to p0.4; uart rx0 is always assigned to p0.5. standard port i/os appear contiguously after the prioritized functions have been assigned. figure 22.4 and figure 22.5 show examples of how the crossbar assigns peripherals according to the xbrn and pnskip register settings. important note: the spi can be operated in either 3-wire or 4-wire modes, pending the state of the nssmd1?nssmd0 bits in register spi0cn. according to the spi mode, the nss signal may or may not be routed to a port pin. table 22.3. port i/o assignment for external digital event capture functions digital function potentially assignable port pins sfr(s) used for assignment external interrupt 0 p0.0 - p0.7 it01cf external interrupt 1 p0.0 - p0.7 it01cf port match p0.0 - p1.7 p0mask, p0mat p1mask, p1mat c8051t620/621/320/321/322/323 138 rev. 1.1 figure 22.3. priority crossbar decoder potential pin assignments 0 p0 port pin number special function signals 0 0 0 0 0 0 0 0 p0skip pin skip settings 1 2 xtal1 3 xtal2 4 5 6 cnvstr 7 vref 0 p1 0 0 0 0 0 0 0 0 p1skip 1 2 3 4 5 6 7 vpp 0 p2 1 0 0 0 0 0 0 0 0 p2skip 1 2 3 4 5 6 7 0 p3 signal unavailable to crossbar pins p0.0-p2.7 1 are capable of being assigned to crossbar peripherals. the crossbar peripherals are assi gned in priority order from top to bottom, according to this diagram. these boxes represent port pins which can potentially be assigned to a peripheral. special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar should be manually configured to skip the corresponding port pins. pins can be ?skipped? by setting the corresponding bit in pnskip to ?1?. notes: 1. p2.4-p2.7 are only available in certain packages. 2. nss is only pinned out when the spi is in 4-wire mode. tx0 rx0 sda scl sysclk cex0 cex1 cex2 eci t0 t1 sck miso mosi nss tx1 rx1 cex3 cex4 cp0 cp0a cp1 cp1a rev. 1.1 139 c8051t620/621/320/321/322/323 figure 22.4. priority crossbar decoder example 1?no skipped pins in this example, the crossbar is configured to assign the uart tx0 and rx0 signals, the spi signals, and three pca signals. note that the spi signals are assigned as multiple signals, and there are no pins skipped using the p0skip or p1skip registers. these boxes represent the port pins which are used by the peripherals in this configuration. 1 st tx0 is assigned to p0.4 2 nd rx0 is assigned to p0.5 3 rd sck, miso, mosi, and nss are assigned to p0.0, p0.1, p0.2, and p0.3, respectively. 4 th cex0, cex1, and cex2 are assigned to p0.6, p0.7, and p1.0, respectively. all unassigned pins can be used as gpio or for other non-crossbar functions. notes: 1. p2.4-p2.7 are only available in certain packages. 0 p0 port pin number special function signals 0 0 0 0 0 0 0 0 p0skip pin skip settings 1 2 xtal1 3 xtal2 4 5 6 cnvstr 7 vref 0 p1 0 0 0 0 0 0 0 0 p1skip 1 2 3 4 5 6 7 vpp 0 p2 1 0 0 0 0 0 0 0 0 p2skip 1 2 3 4 5 6 7 0 p3 signal unavailable to crossbar tx0 rx0 sda scl sysclk cex0 cex1 cex2 eci t0 t1 sck miso mosi nss tx1 rx1 cex3 cex4 cp0 cp0a cp1 cp1a c8051t620/621/320/321/322/323 140 rev. 1.1 figure 22.5. priority crossbar decoder example 2?skipping pins in this example, the crossbar is configured to assign the uart tx0 and rx0 signals, the spi signals, and three pca signals. note that the spi signals are assigned as multiple signals. additionally, pins p0.0, p0.2, and p0.3 are configured to be skipped using the p0skip register. these boxes represent the port pins which are used by the peripherals in this configuration. 1 st tx0 is assigned to p0.4 2 nd rx0 is assigned to p0.5 3 rd sck, miso, mosi, and nss are assigned to p0.1, p0.6, p0.7, and p1.0, respectively. 4 th cex0, cex1, and cex2 are assigned to p1.1, p1.2, and p1.3, respectively. all unassigned pins, including those skipped by xbr0 can be used as gpio or for other non- crossbar functions. notes: 1. p2.4-p2.7 are only available in certain packages. 0 p0 port pin number special function signals 1 0 1 1 0 0 0 0 p0skip pin skip settings 1 2 xtal1 3 xtal2 4 5 6 cnvstr 7 vref 0 p1 0 0 0 0 0 0 0 0 p1skip 1 2 3 4 5 6 7 vpp 0 p3 signal unavailable to crossbar p0.0 skipped p0.3 skipped p0.2 skipped tx0 rx0 sda scl sysclk cex0 cex1 cex2 eci t0 t1 sck miso mosi nss tx1 rx1 cex3 cex4 cp0 cp0a cp1 cp1a 0 p2 1 0 0 0 0 0 0 0 0 p2skip 1 2 3 4 5 6 7 rev. 1.1 141 c8051t620/621/320/321/322/323 22.4. port i/o initialization port i/o initialization cons ists of the following steps: 1. select the input mode (analog or digital) for all port pins, using the port input mode register (pnmdin). 2. select the output mode (open-drain or push-pull) fo r all port pins, using the port output mode register (pnmdout). 3. select any pins to be skipped by the i/o cr ossbar using the port skip registers (pnskip). 4. assign port pins to desired peripherals (xbr0, xbr1, xbr2). 5. enable the cro ssbar (xbare = 1). all port pins must be configured as either analog or digital inputs. any pins to be used as comparator or adc inputs should be configured as an analog inputs. when a pin is configured as an analog input, its weak pullup, digital driver, and digital receiver are disabled. this process save s power and reduces noise on the analog input. pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. additionally, all analog input pins should be configur ed to be skipped by the crossbar (accomplished by setting the associated bits in pnskip). port input mode is set in the pnmdin register, where a 1 indicates a digital input, and a 0 indicates an analog input. all pins default to digital inputs on reset. see sfr definition 22.9, sfr definition 22.13, and sfr definition 22.17 for the pnmdin register details. the output driver characteristics of the i/o pins ar e defined using the port output mode registers (pnmd- out). each port output driver can be configured as either open drain or push- pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. when the weakpud bit in xbr1 is 0, a weak pullup is enabled for all po rt i/o config- ured as open-drain. weakpu d does not affect the pu sh-pull port i/o. furthe rmore, the weak pullup is turned off on an output that is driving a 0 to avoid unnecessary power dissipation. registers xbr0, xbr1, and xbr2 must be loaded with t he appropriate values to select the digital i/o functions required by the design. setting the xbare bit in xbr1 to 1 enables the crossbar. until the crossbar is enabled, the external pins remain as standard port i/o (in input mode), regardless of the xbrn register settings. for given xbrn register settings, on e can determine the i/o pin-out using the priority decode table; as an alternative, the configuration wizard utility of the silicon labs ide software will deter- mine the port i/o pin-assignments based on the xbrn register settings. the crossbar must be enabled to us e port pins as standard port i/o in output mode. port output drivers are disabled while the crossbar is disabled. c8051t620/621/320/321/322/323 142 rev. 1.1 sfr address = 0xe1 sfr definition 22.1. xbr0: port i/o crossbar register 0 bit76543210 name cp1ae cp1e cp0ae cp0e syscke smb0e spi0e urt0e type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7cp1ae comparator1 asynchronous output enable. 0: asynchronous cp1 unavailable at port pin. 1: asynchronous cp1 routed to port pin. 6cp1e comparator1 output enable. 0: cp1 unavailable at port pin. 1: cp1 routed to port pin. 5cp0ae comparator0 asynchronous output enable. 0: asynchronous cp0 unavailable at port pin. 1: asynchronous cp0 routed to port pin. 4cp0e comparator0 output enable. 0: cp0 unavailable at port pin. 1: cp0 routed to port pin. 3 syscke /sysclk output enable. the source of this signal is determined by the outclk bit (see sfr definition 21.1). 0: /sysclk unavaila ble at port pin. 1: /sysclk output r outed to port pin. 2smb0e smbus i/o enable. 0: smbus i/o unavailable at port pins. 1: smbus i/o routed to port pins. 1spi0e spi i/o enable. 0: spi i/o unavailable at port pins. 1: spi i/o routed to port pins. note that the spi can be assigned either 3 or 4 gpio pins. 0urt0e uart i/o output enable. 0: uart i/o unavailable at port pin. 1: uart tx0, rx0 routed to port pins p0.4 and p0.5. rev. 1.1 143 c8051t620/621/320/321/322/323 sfr address = 0xe2 sfr definition 22.2. xbr1: port i/o crossbar register 1 bit7 6543210 name weakpud xbare t1e t0e ecie pca0me[2:0] type r/w r/w r/w r/w r/w r/w reset 0 0000000 bit name function 7 weakpud port i/o weak pullup disable. 0: weak pullups enabled (except for ports whose i/o are configured for analog mode). 1: weak pullups disabled. 6 xbare crossbar enable. 0: crossbar disabled. 1: crossbar enabled. 5t1e t1 enable. 0: t1 unavailable at port pin. 1: t1 routed to port pin. 4t0e t0 enable. 0: t0 unavailable at port pin. 1: t0 routed to port pin. 3ecie pca0 external counter input enable. 0: eci unavailable at port pin. 1: eci routed to port pin. 2:0 pca0me[2:0] pca module i/o enable bits. 000: all pca i/o unavailable at port pins. 001: cex0 routed to port pin. 010: cex0, cex1 routed to port pins. 011: cex0, cex1, cex2 routed to port pins. 100: cex0, cex1, cex2, cex3 routed to port pins. 101: cex0, cex1, cex2, cex3, cex4 routed to port pins. 110-111: reserved. c8051t620/621/320/321/322/323 144 rev. 1.1 sfr address = 0xe3 22.5. port match port match functionality allows system events to be tr iggered by a logic value change on p0 or p1. a soft- ware controlled value stored in the pnmatch registers specifies the expected or normal logic values of p0 and p1. a port mismatch event occurs if the logic levels of the port?s input pins no longer match the soft- ware controlled value. this allows software to be notified if a certain change or pattern occurs on p0 or p1 input pins regardless of the xbrn settings. the pnmask registers can be used to individually select which p0 a nd p1 pins should be compared against the pnmatch regist ers. a port mismatch event is gene rated if (p0 & p0m ask) does not equal (p0match & p0mask) or if (p1 & p1mask) does not equal (p1match & p1mask). a port mismatch event may be used to generate an interrupt or wake the device from a low power mode, such as idle or suspend. see the interrupts and power options chapte rs for more details on interrupt and wake-up sources. sfr definition 22.3. xbr2: port i/o crossbar register 2 bit7 6543210 name urt1e type r rrrrrrr/w reset 0 0000000 bit name function 7:1 unused unused. read = 0000000b; write = don?t care. 0urt1e uart1 i/o output enable bit. 0: uart1 i/o unavailable at port pins. 1: uart1 tx1, rx1 routed to port pins. rev. 1.1 145 c8051t620/621/320/321/322/323 sfr address = 0xae sfr address = 0x84 sfr definition 22.4. p0mask : port 0 mask register bit76543210 name p0mask[7:0] type r/w reset 00000000 bit name function 7:0 p0mask[7:0] port 0 mask value. selects p0 pins to be compared to the corresponding bits in p0mat. 0: p0.n pin logic value is ignored an d cannot cause a port mismatch event. 1: p0.n pin logic value is compared to p0mat.n. sfr definition 22.5. p0mat: port 0 match register bit76543210 name p0mat[7:0] type r/w reset 11111111 bit name function 7:0 p0mat[7:0] port 0 match value. match comparison value used on port 0 for bits in p0mask which are set to 1. 0: p0.n pin logic value is compared with logic low. 1: p0.n pin logic value is compared with logic high. c8051t620/621/320/321/322/323 146 rev. 1.1 sfr address = 0xba sfr address = 0xb6 22.6. special function re gisters for accessing an d configuring port i/o all port i/o are accessed through corresponding specia l function registers (sfrs) that are both byte addressable and bit addressable. when writing to a port, the value writt en to the sfr is latched to main- tain the output data value at each pin. when reading, the logic levels of the port's input pins are returned regardless of the xbrn settings (i.e., even when the pi n is assigned to another signal by the crossbar, the port register can always read its corresponding port i/ o pin). the exception to this is the execution of the read-modify-write instructio ns that target a port latch register as the destination. the read-modify-write instructions when operating on a port sfr are the fo llowing: anl, orl, xrl, jb c, cpl, inc, dec, djnz and mov, clr or setb, when the destination is an indi vidual bit in a port sfr. for these instructions, the value of the latch register (not the pin) is read, modified, and written back to the sfr. each port has a corresponding pnskip register which allo ws its individual port pins to be assigned to dig- ital functions or skipped by the crossbar. all port pins used for analog functions or gpio should have their pnskip bit set to 1. sfr definition 22.6. p1mask : port 1 mask register bit76543210 name p1mask[7:0] type r/w reset 00000000 bit name function 7:0 p1mask[7:0] port 1 mask value. selects p1 pins to be compared to the corresponding bits in p1mat. 0: p1.n pin logic value is ignored an d cannot cause a port mismatch event. 1: p1.n pin logic value is compared to p1mat.n. sfr definition 22.7. p1mat: port 1 match register bit76543210 name p1mat[7:0] type r/w reset 11111111 bit name function 7:0 p1mat[7:0] port 1 match value. match comparison value used on port 1 for bits in p1mask which are set to 1. 0: p1.n pin logic value is compared with logic low. 1: p1.n pin logic value is compared with logic high. rev. 1.1 147 c8051t620/621/320/321/322/323 the port input mode of the i/o pins is defined usi ng the port input mode registers (pnmdin). each port cell can be configured for analog or digital i/o. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. th e only exception to this is p3.0, which can only be used for digital i/o. the output driver characteristics of the i/o pins ar e defined using the port output mode registers (pnmd- out). each port output driver can be configured as either open drain or push- pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. sfr address = 0x80; bit-addressable sfr definition 22.8. p0: port 0 bit76543210 name p0[7:0] type r/w reset 11111111 bit name description write read 7:0 p0[7:0] port 0 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p0.n port pin is logic low. 1: p0.n port pin is logic high. c8051t620/621/320/321/322/323 148 rev. 1.1 sfr address = 0xf1 sfr address = 0xa4 sfr definition 22.9. p0md in: port 0 input mode bit76543210 name p0mdin[7:0] type r/w reset 11111111 bit name function 7:0 p0mdin[7:0] analog configuration bits for p0.7?p0.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p0.n pin is configured for analog mode. 1: corresponding p0.n pin is not configured for analog mode. sfr definition 22.10. p0md out: port 0 output mode bit76543210 name p0mdout[7:0] type r/w reset 00000000 bit name function 7:0 p0mdout[7:0] output configuration bits for p0.7?p0.0 (respectively). these bits are ignored if the corresponding bit in register p0mdin is logic 0. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull. rev. 1.1 149 c8051t620/621/320/321/322/323 sfr address = 0xd4 sfr address = 0x90; bit-addressable sfr definition 22.11. p0skip: port 0 skip bit76543210 name p0skip[7:0] type r/w reset 00000000 bit name function 7:0 p0skip[7:0] port 0 crossbar skip enable bits. these bits select port 0 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p0.n pin is not skipped by the crossbar. 1: corresponding p0.n pin is skipped by the crossbar. sfr definition 22.12. p1: port 1 bit76543210 name p1[7:0] type r/w reset 11111111 bit name description write read 7:0 p1[7:0] port 1 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p1.n port pin is logic low. 1: p1.n port pin is logic high. c8051t620/621/320/321/322/323 150 rev. 1.1 sfr address = 0xf2 sfr address = 0xa5 sfr definition 22.13. p1 mdin: port 1 input mode bit76543210 name p1mdin[7:0] type r/w reset 11111111 bit name function 7:0 p1mdin[7:0] analog configuration bits for p1.7?p1.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p1.n pin is configured for analog mode. 1: corresponding p1.n pin is not configured for analog mode. sfr definition 22.14. p1md out: port 1 output mode bit76543210 name p1mdout[7:0] type r/w reset 00000000 bit name function 7:0 p1mdout[7:0] output configuration bits for p1.7?p1.0 (respectively). these bits are ignored if the corresponding bit in register p1mdin is logic 0. 0: corresponding p1.n output is open-drain. 1: corresponding p1.n output is push-pull. rev. 1.1 151 c8051t620/621/320/321/322/323 sfr address = 0xd5 sfr address = 0xa0; bit-addressable sfr definition 22.15. p1skip: port 1 skip bit76543210 name p1skip[7:0] type r/w reset 00000000 bit name function 7:0 p1skip[7:0] port 1 crossbar skip enable bits. these bits select port 1 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p1.n pin is not skipped by the crossbar. 1: corresponding p1.n pin is skipped by the crossbar. sfr definition 22.16. p2: port 2 bit76543210 name p2[7:0] type r/w reset 11111111 bit name description write read 7:0 p2[7:0] port 2 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p2.n port pin is logic low. 1: p2.n port pin is logic high. c8051t620/621/320/321/322/323 152 rev. 1.1 sfr address = 0xf3 sfr address = 0xa6 sfr definition 22.17. p2 mdin: port 2 input mode bit76543210 name p2mdin[7:0] type r/w reset 11111111 bit name function 7:0 p2mdin[7:0] analog configuration bits for p2.7?p2.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p2.n pin is configured for analog mode. 1: corresponding p2.n pin is not configured for analog mode. sfr definition 22.18. p2md out: port 2 output mode bit76543210 name p2mdout[7:0] type r/w reset 00000000 bit name function 7:0 p2mdout[7:0] output configuration bits for p2.7?p2.0 (respectively). these bits are ignored if the corresponding bit in register p2mdin is logic 0. 0: corresponding p2.n output is open-drain. 1: corresponding p2.n output is push-pull. rev. 1.1 153 c8051t620/621/320/321/322/323 sfr address = 0xd6 sfr address = 0xb0; bit-addressable sfr definition 22.19. p2skip: port 2 skip bit76543210 name p2skip[7:0] type r/w reset 00000000 bit name function 7:0 p2skip[7:0] port 2 crossbar skip enable bits. these bits select port 2 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p2.n pin is not skipped by the crossbar. 1: corresponding p2.n pin is skipped by the crossbar. sfr definition 22.20. p3: port 3 bit76543210 name p3[0] type rrrrrrrr/w reset 00000001 bit name description write read 7:1 unused unused. don?t care 0000000b 0 p3[0] port 3 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p3.0 port pin is logic low. 1: p3.0 port pin is logic high. c8051t620/621/320/321/322/323 154 rev. 1.1 sfr address = 0xa7 sfr definition 22.21. p3md out: port 3 output mode bit7654321 0 name p3mdout[0] type rrrrrrr r/w reset 0000000 0 bit name function 7:1 unused unused. read = 0000000b; write = don?t care 0p3mdout[0] output configuration bits for p3.0. 0: p3.0 output is open-drain. 1: p3.0 output is push-pull. rev. 1.1 155 c8051t620/621/320/321/322/323 23. universal serial bus controller (usb0) c8051t620/621/320/321/322/323 devices include a complete full/low speed usb function for usb peripheral implementations. the usb function controlle r (usb0) consists of a serial interface engine (sie), usb transceiver (including matching resistors and configurable pull-up resistors), 1 kb fifo block, and clock recovery mechanism for crystal-less operation. no external components are required. the usb function controller and transceiver is univer sal serial bus specification 2.0 compliant. figure 23.1. usb0 block diagram important note: this document assumes a comprehe nsive understanding of the usb protocol. terms and abbreviations used in this document are defined in the usb specification. we encourage you to review the latest version of the usb specification before proceeding. note: the c8051t620/621/320/321/322/323 cannot be used as a usb host device. 23.1. endpoint addressing a total of eight endpoint pipes are available. the c ontrol endpoint (endpoint0) always functions as a bi- directional in/out endpoint. the other endpoints ar e implemented as three pairs of in/out endpoint pipes: transceiver serial interface engine (sie) usb fifos (1k ram) d+ d- vdd endpoint0 in/out endpoint1 in out endpoint2 in out endpoint3 in out data transfer control cip-51 core usb control, status, and interrupt registers c8051t620/621/320/321/322/323 156 rev. 1.1 23.2. usb transceiver the usb transceiver is configured via the usb0xcn register shown in sfr definition 23.1. this configu- ration includes transceiver enable/disable, pull-up resistor enable/disable, and device speed selection (full or low speed). when bit speed = 1, usb0 operates as a full speed usb function, and the on-chip pull-up resistor (if enabled) appears on the d+ pin. when bit speed = 0, usb0 operates as a low speed usb function, and the on-chip pull-up resistor (if ena bled) appears on the d- pin. bits4-0 of register usb0xcn can be used for transceiver testing as described in sfr definition 23.1. the pull-up resistor is enabled only when vbus is present (see section ?1 1.1.2. vbus detection? on page 59 for details on vbus detection). important note: the usb clock should be active before the transceiver is enabled. table 23.1. endpoint addressing scheme endpoint associated pipes usb protocol address endpoint0 endpoint0 in 0x00 endpoint0 out 0x00 endpoint1 endpoint1 in 0x81 endpoint1 out 0x01 endpoint2 endpoint2 in 0x82 endpoint2 out 0x02 endpoint3 endpoint3 in 0x83 endpoint3 out 0x03 rev. 1.1 157 c8051t620/621/320/321/322/323 sfr address = 0xd7 sfr definition 23.1. usb0xcn: usb0 transceiver control bit76543210 name pren phyen speed phytst[1:0] dfrec dp dn type r/w r/w r/w r/w r r r reset 00000000 bit name function 7pren internal pull-up resistor enable. the location of the pull-up resistor (d+ or d-) is de termined by the speed bit. 0: internal pull-up resistor disabled (device effectively detached from usb network). 1: internal pull-up resistor enabled when vbus is present (device attached to the usb network). 6 phyen physical layer enable. 0: usb0 physical layer transceiver disabled (suspend). 1: usb0 physical layer tran sceiver enabled (normal). 5 speed usb0 speed select. this bit selects the usb0 speed. 0: usb0 operates as a low speed device. if enabled, the internal pull-up resistor appears on the d? line. 1: usb0 operates as a full speed device. if enabled, the internal pull-up resistor appears on the d+ line. 4:3 phytst[1:0] physical layer test bits. 00: mode 0: normal (non-test mode) (d+ = x, d- = x) 01: mode 1: differential 1 forced (d+ = 1, d- = 0) 10: mode 2: differential 0 forced (d+ = 0, d- = 1) 11: mode 3: single-ended 0 forced (d+ = 0, d? = 0) 2dfrec differential receiver bit the state of this bit indicates the current differential value present on the d+ and d- lines when phyen = 1. 0: differential 0 signalling on the bus. 1: differential 1 signalling on the bus. 1dp d+ signal status. this bit indicates the curren t logic level of the d+ pin. 0: d+ signal currently at logic 0. 1: d+ signal currently at logic 1. 0dn d? signal status. this bit indicates the curren t logic level of the d- pin. 0: d? signal currently at logic 0. 1: d? signal currently at logic 1. c8051t620/621/320/321/322/323 158 rev. 1.1 23.3. usb register access the usb0 controller registers listed in table 23 .2 are accessed through two sfrs: usb0 address (usb0adr) and usb0 data (usb0dat). the usb0adr register se lects which usb register is targeted by reads/writes of the usb0 dat register. see figure 23.2. endpoint control/status registers ar e accessed by first writing the usb re gister index with the target end- point number. once the target endpoint number is writ ten to the index register, the control/status registers associated with the target endpoint may be accessed. see the ?indexed registers? section of table 23.2 for a list of endpoint control/status registers. important note : the usb clock must be active when accessing usb registers. figure 23.2. usb0 register access scheme usb controller fifo access index register endpoint0 control/ status registers endpoint1 control/ status registers endpoint2 control/ status registers endpoint3 control/ status registers common registers interrupt registers 8051 sfrs usb0adr usb0dat rev. 1.1 159 c8051t620/621/320/321/322/323 sfr address = 0x96 sfr definition 23.2. usb0adr : usb0 indirect address bit76543210 name busy autord usbaddr[5:0] type r/w r/w r/w reset 00000000 bit name description write read 7busy usb0 register read busy flag. this bit is used during indirect usb0 register accesses. 0: no effect. 1: a usb0 indirect regis- ter read is initiated at the address specified by the usbaddr bits. 0: usb0dat register data is valid. 1: usb0 is busy access- ing an indirect register; usb0dat register data is invalid. 6autord usb0 register auto-read flag. this bit is used for block fifo reads. 0: busy must be written manually for each usb0 indirect register read. 1: the next indirect regi ster read will automatically be initiated when software reads usb0dat (usbaddr bits will not be changed). 5:0 usbaddr[5:0] usb0 indirect register address bits. these bits hold a 6-bit address used to indirectly access the usb0 core registers. table 23.2 lists the usb0 core register s and their indirect addresses. reads and writes to usb0dat will target the regi ster indicated by the usbaddr bits. c8051t620/621/320/321/322/323 160 rev. 1.1 sfr address = 0x97 sfr definition 23.3. usb0dat: usb0 data bit76543210 name usb0dat[7:0] type r/w reset 00000000 bit name description write read 7:0 usb0dat[7:0] usb0 data bits. this sfr is used to indi- rectly read and write usb0 registers. write procedure: 1. poll for busy (usb0adr.7) => 0. 2. load the target usb0 register address into the usbaddr bits in register usb0adr. 3. write data to usb0dat. 4. repeat (step 2 may be skipped when writing to the same usb0 register). read procedure: 1. poll for busy (usb0adr.7) => 0. 2. load the target usb0 register address into the usbaddr bits in register usb0adr. 3. write 1 to the busy bit in register usb0adr (steps 2 and 3 can be per- formed in the same write). 4. poll for busy (usb0adr.7) => 0. 5. read data from usb0dat. 6. repeat from step 2 (step 2 may be skipped when reading the same usb0 register; step 3 may be skipped when the autord bit (usb0adr.6) is logic 1). rev. 1.1 161 c8051t620/621/320/321/322/323 table 23.2. usb0 controller registers usb register name usb register address description page number interrupt registers in1int 0x02 endpoint0 and endpoints1-3 in interrupt flags 170 out1int 0x04 endpoints1-3 out interrupt flags 171 cmint 0x06 common usb interrupt flags 172 in1ie 0x07 endpoint0 and endpoints1-3 in interrupt enables 173 out1ie 0x09 endpoints1-3 out interrupt enables 174 cmie 0x0b common usb in terrupt enables 175 common registers faddr 0x00 function address 166 power 0x01 power management 168 framel 0x0c frame number low byte 169 frameh 0x0d frame number high byte 169 index 0x0e endpoint index selection 162 clkrec 0x0f clock recovery control 163 eenable 0x1e endpoint enable 180 fifon 0x20-0x23 endpoints0-3 fifos 165 indexed registers e0csr 0x11 endpoint0 control / status 178 eincsrl endpoint in control / status low byte 182 eincsrh 0x12 endpoint in control / status high byte 183 eoutcsrl 0x14 endpoint out control / status low byte 185 eoutcsrh 0x15 endpoint out co ntrol / status high byte 186 e0cnt 0x16 number of received bytes in endpoint0 fifo 179 eoutcntl endpoint out packet count low byte 186 eoutcnth 0x17 endpoint out packet count high byte 187 c8051t620/621/320/321/322/323 162 rev. 1.1 usb register address = 0x0e 23.4. usb clock configuration usb0 is capable of communication as a full or low speed usb function. communication speed is selected via the speed bit in sfr usb0xcn. when operati ng as a low speed func tion, the usb0 clock must be 6 mhz. when operating as a full speed functi on, the usb0 clock must be 48 mhz. clock options are described in section ?21. oscillators and clock selection? on page 122. the u sb0 clock is selected via sfr clksel (see sfr definition 21.1). clock recovery circuitry uses the inco ming usb data stream to adjust the internal oscillato r; this allows the internal oscillator to meet the re quirements for usb clock tolerance. clock recovery should be used in the following configurations: when operating usb0 as a low speed function with clock recovery, software must write 1 to the crlow bit to enable low speed clock reco very. clock recovery is typically not necessary in low speed mode. single step mode can be used to help the clock reco very circuitry to lock when high noise levels are pres- ent on the usb network. this mode is not requir ed (or recommended) in typical usb environments. usb register definition 23.4. index: usb0 endpoint index bit76543210 name epsel[3:0] type rrrr r/w reset 00000000 bit name function 7:4 unused unused. read = 0000b. write = don?t care. 3:0 epsel[3:0] endpoint select bits. these bits select which endpoint is targeted when indexed usb0 registers are accessed. 0000: endpoint 0 0001: endpoint 1 0010: endpoint 2 0011: endpoint 3 0100-1111: reserved. communication speed usb clock full speed internal oscillator low speed interna l oscillator / 8 rev. 1.1 163 c8051t620/621/320/321/322/323 usb register address = 0x0f 23.5. fifo management 1024 bytes of on-chip xram are used as fifo sp ace for usb0. this fifo space is split between endpoints0-3 as shown in figure 23.3. fifo space allo cated for endpoints1-3 is configurable as in, out, or both (split mode: half in, half out). usb register definition 23.5. clkrec: clock recovery control bit76543210 name cre crssen crlow reserved reserv ed reserved reserved reserved type r/w r/w r/w r/w r/w r/w r/w r/w reset 00001111 bit name function 7 cre clock recovery enable bit. this bit enables/disables the usb clock recovery feature. 0: clock recovery disabled. 1: clock recovery enabled. 6 crssen clock recovery single step. this bit forces the oscillator calibration into ?single-step? mode during clock recovery. 0: normal calib ration mode. 1: single step mode. 5crlow low speed clock recovery mode. this bit must be set to 1 if clock recovery is used when operating as a low speed usb device. 0: full speed mode. 1: low speed mode. 4:0 reserved reserved. read = variable. must write = 01111b. c8051t620/621/320/321/322/323 164 rev. 1.1 figure 23.3. usb fifo allocation 23.5.1. fifo split mode the fifo space for endpoints1-3 can be split such that the upper half of the fifo space is used by the in endpoint, and the lower half is used by the out endpoint . for example: if the end point3 fifo is configured for split mode, the upper 256 bytes (0x0540 to 0x063f) are used by endpoint3 in and the lower 256 bytes (0x0440 to 0x053f) are used by endpoint3 out. if an endpoint fifo is not configured for split mode , that endpoint in/out pair?s fifos are combined to form a single in or out fifo. in this case only one direction of the endpoint in/out pair may be used at a time. the endpoint direction (in/out) is determined by the dirsel bit in the corresponding endpoint?s eincsrh register (see sfr definition 23.13). 23.5.2. fifo double buffering fifo slots for endpoints1-3 can be configured for double-buffered mode. in this mode, the maximum packet size is halved and the fifo may contain tw o packets at a time. this mode is available for endpoints1-3. when an endpoint is configured for split mode, double buffering may be enabled for the in endpoint and/or the out endpoint. when split mode is not enabled, double-buffering may be enabled for the entire endpoint fifo. see table 23.3 for a list of maximum packet sizes for each fifo configuration. endpoint0 (64 bytes) configurable as in, out, or both (split mode) free (64 bytes) 0x0400 0x043f 0x0440 0x063f 0x0640 0x073f 0x0740 0x07bf 0x07c0 0x07ff user xram (1024 bytes) 0x0000 0x03ff usb clock domain system clock domain endpoint1 (128 bytes) endpoint2 (256 bytes) endpoint3 (512 bytes) rev. 1.1 165 c8051t620/621/320/321/322/323 23.5.1. fifo access each endpoint fifo is accessed through a correspond ing fifon register. a read of an endpoint fifon register unloads one byte from the fifo; a write of an endpoi nt fifon register loads one byte into the end- point fifo. when an endpoint fifo is configured for split mode, a read of the endpoint fifon register unloads one byte from the out endpoint fifo; a write of the endpoint fifon register loads one byte into the in endpoint fifo. usb register address = 0x20-0x23 table 23.3. fifo configurations endpoint number split mode enabled? maximum in packet size (double buffer disabled / enabled) maximum out packet size (double buffer disabled / enabled) 0n/a 64 1 n 128 / 64 y 64 / 32 64 / 32 2 n 256 / 128 y 128 / 64 128 / 64 3 n 512 / 256 y 256 / 128 256 / 128 usb register definition 23.6. fi fon: usb0 endpoint fifo access bit76543210 name fifodata[7:0] type r/w reset 00000000 bit name function 7:0 fifodata[7:0] endpoint fifo access bits. usb addresses 0x20-0x23 provide access to the 4 pairs of endpoint fifos: 0x20: endpoint 0 0x21: endpoint 1 0x22: endpoint 2 0x23: endpoint 3 writing to the fifo address loads data into the in fifo for the corresponding endpoint. reading from the fifo address unloads data from the out fifo for the corresponding endpoint. c8051t620/621/320/321/322/323 166 rev. 1.1 23.6. function addressing the faddr register holds the current usb0 function address. software should write the host-assigned 7- bit function address to the faddr register when received as pa rt of a set_address command. a new address written to faddr will not take effect (usb0 will not respond to the new ad dress) until the end of the current transfer (typic ally following the status phase of the set_address command transfer). the update bit (faddr.7) is set to 1 by hardware when software writes a new address to the faddr regis- ter. hardware clears the update bit when the new address takes effect as described above. usb register address = 0x00 23.7. function configuration and control the usb register power (usb register definition 23. 8) is used to configure and control usb0 at the device level (enable/disable, rese t/suspend/resume handling, etc.). usb reset: the usbrst bit (power.3) is set to 1 by hardware when reset signaling is detected on the bus. upon this detect ion, the following occur: 1. the usb0 address is reset (faddr = 0x00). 2. endpoint fifos are flushed. 3. control/status registers are reset to 0x00 (e0csr, eincsrl, eincsrh, eoutcsrl, eoutcsrh). 4. usb register index is reset to 0x00. 5. all usb interrupts (excluding the suspend interrupt) are enabled and their corresponding flags cleared. 6. a usb reset interrupt is generated if enabled. writing a 1 to the usbrst bit will ge nerate an asynchronous usb0 rese t. all usb regist ers are reset to their default values following this asynchronous reset. suspend mode: with suspend detection enabled (susen = 1), usb0 will enter suspend mode when suspend signaling is detected on th e bus. an interrupt will be generat ed if enabled (susinte = 1). the suspend interrupt service routine (isr) should perfor m application-specific conf iguration tasks such as usb register definition 23.7. faddr: usb0 function address bit76543210 name update faddr[6:0] type rr/w reset 00000000 bit name function 7update function address update bit. set to 1 when software writes the faddr regi ster. usb0 clears this bit to 0 when the new address takes effect. 0: the last address written to faddr is in effect. 1: the last address written to faddr is not yet in effect. 6:0 faddr[6:0] function address bits. holds the 7-bit function address for usb0. this address should be written by software when the set_address standard device re quest is received on endpoint0. the new address takes effect when the device request completes. rev. 1.1 167 c8051t620/621/320/321/322/323 disabling appropriate peripherals and/or configuring clock sources for low power modes. see section ?21.3. programmable internal high-f requency (h-f) oscillator? on page 125 for more details on internal oscillator configuration, incl uding the suspend mode feature of the internal oscillator. usb0 exits suspend mode when any of the following occur: (1) resume signaling is detected or gener- ated, (2) reset signaling is detected, or (3) a device or usb reset occurs. if susp ended, the internal oscil- lator will exit suspend mode upon any of the above listed events. resume signaling: usb0 will exit suspend mode if resume signaling is detected on the bus. a resume interrupt will be gener ated upon detect ion if enabled (resinte = 1). software may force a remote wakeup by writing 1 to the resume bit (power.2). when forcing a remote wakeup, software should write resume = 0 to end resume signaling 10-15 ms after the remote wakeup is initiated (resume = 1). iso update: when software writes 1 to the isoup bit (p ower.7), the iso update function is enabled. with iso update enabled, new packe ts written to an iso in endpoint will not be transmitted until a new start-of-frame (sof) is re ceived. if the iso in endpoint receives an in token before a sof, usb0 will transmit a zero-length packet. when isoup = 1, iso update is enabled for all iso endpoints. usb enable: usb0 is disabled following a power-on-reset (por). usb0 is enabled by clearing the usbinh bit (power.4). once written to 0, the usbinh can only be set to 1 by one of the following: (1) a power-on-reset (por), or (2) an asynchronous usb0 reset generated by writing 1 to the usbrst bit (power.3). software should perform all usb0 configuration before enabling usb0. the configuration sequence should be performed as follows: 1. select and enable the usb clock source. 2. reset usb0 by writing usbrst= 1. 3. configure and enable the usb transceiver. 4. perform any usb0 function configur ation (interrupts, suspend detect). 5. enable usb0 by writing usbinh = 0. c8051t620/621/320/321/322/323 168 rev. 1.1 usb register address = 0x01 usb register definition 23. 8. power: usb0 power bit76543210 name isoud usbinh usbrst resume susmd susen type r/w r/w r/w r/w r/w r/w r r/w reset 00010000 bit name function 7isoud iso update bit. this bit affects all in isochronous endpoints. 0: when software writes inprdy = 1, usb0 will send the packet when the next in token is received. 1: when software writes inprdy = 1, usb0 will wait for a sof toke n before s ending the packet. if an in token is rece ived before a sof token, u sb0 will send a zero-length data packet. 6:5 unused unused. read = 00b. write = don?t care. 4 usbinh usb0 inhibit bit. this bit is set to 1 following a power-on reset (por) or an asynchronous usb0 reset. software should clear this bit after all usb0 transceiver initializat ion is complete. soft- ware cannot set this bit to 1. 0: usb0 enabled. 1: usb0 inhibited. all usb traffic is ignored. 3 usbrst reset detect. read: 0: reset signaling is not present. 1: reset signaling detected on the bus. write: writing 1 to this bit forces an asynchronous usb0 reset. 2 resume force resume. writing a 1 to this bit while in suspend mode (susmd = 1) forces usb0 to generate resume signaling on the bus (a remote wakeup event). software should write resume = 0 after 10 to 15 ms to end the resume signaling. an interrupt is generated, and hard- ware clears susmd, when so ftware writes resume = 0. 1susmd suspend mode. set to 1 by hardware when usb0 enters suspend mode. cleared by hardware when soft- ware writes resume = 0 (following a remote wakeup) or reads the cmint register after detection of resume signaling on the bus. 0: usb0 not in suspend mode. 1: usb0 in suspend mode. 0 susen suspend detection enable. 0: suspend detection disabled. usb0 will ignore su spend signaling on the bus. 1: suspend detection enabled. usb0 will enter suspend mode if it detects suspend sig- naling on the bus. rev. 1.1 169 c8051t620/621/320/321/322/323 usb register address = 0x0c usb register address = 0x0d 23.8. interrupts the read-only usb0 interrupt flags are located in the usb registers shown in usb register definition 23.11 through usb register definition 23.13. the associated interrupt enable bits are located in the usb registers shown in usb regist er definition 23.14 through usb re gister definition 23.16. a usb0 interrupt is generated when any of the usb interrupt flag s is set to 1. the usb0 interrupt is enabled via the eie1 sfr (see section ?17. interrupts? on page 96). important note: reading a usb interrupt flag register resets all flags in that register to 0. usb register definition 23.9. framel: usb0 frame number low bit76543210 name frmel[7:0] type r reset 00000000 bit name function 7:0 frmel[7:0] frame number low bits. this register contains bits 7-0 of the last received frame number. usb register definition 23.10. fr ameh: usb0 frame number high bit76543210 name frmeh[2:0] type rrrrr r reset 00000000 bit name function 7:3 unused unused. read = 00000b. write = don?t care. 2:0 frmeh[2:0] frame number high bits. this register contains bits 10-8 of the last received frame number. c8051t620/621/320/321/322/323 170 rev. 1.1 usb register address = 0x02 usb register definition 23.11. in1i nt: usb0 in endpoint interrupt bit76543210 name in3 in2 in1 ep0 type rrrrrrrr reset 00000000 bit name function 7:4 unused unused. read = 0000b. write = don?t care. 3in3 in endpoint 3 interrupt-pending flag. this bit is cleared when software reads the in1int register. 0: in endpoint 3 interrupt inactive. 1: in endpoint 3 interrupt active. 2in2 in endpoint 2 interrupt-pending flag. this bit is cleared when software reads the in1int register. 0: in endpoint 2 interrupt inactive. 1: in endpoint 2 interrupt active. 1in1 in endpoint 1 interrupt-pending flag. this bit is cleared when software reads the in1int register. 0: in endpoint 1 interrupt inactive. 1: in endpoint 1 interrupt active. 0 ep0 endpoint 0 interrupt-pending flag. this bit is cleared when software reads the in1int register. 0: endpoint 0 interrupt inactive. 1: endpoint 0 interrupt active. rev. 1.1 171 c8051t620/621/320/321/322/323 usb register address = 0x04 usb register definition 23.12. out1 int: usb0 out endpoint interrupt bit76543210 name out3 out2 out1 type rrrrrrrr reset 00000000 bit name function 7:4 unused unused. read = 0000b. write = don?t care. 3out3 out endpoint 3 interrupt-pending flag. this bit is cleared when softwa re reads the out1int register. 0: out endpoint 3 interrupt inactive. 1: out endpoint 3 interrupt active. 2out2 out endpoint 2 interrupt-pending flag. this bit is cleared when softwa re reads the out1int register. 0: out endpoint 2 interrupt inactive. 1: out endpoint 2 interrupt active. 1out1 out endpoint 1 interrupt-pending flag. this bit is cleared when softwa re reads the out1int register. 0: out endpoint 1 interrupt inactive. 1: out endpoint 1 interrupt active. 0 unused unused. read = 0b. write = don?t care. c8051t620/621/320/321/322/323 172 rev. 1.1 usb register address = 0x06 usb register definition 23.13. cmint: usb0 common interrupt bit76543210 name sof rstint rsuint susint type rrrrrrrr reset 00000000 bit name function 7:4 unused unused. read = 0000b. write = don?t care. 3sof start of frame interrupt flag. set by hardware when a sof token is receiv ed. this interrupt event is synthesized by hardware: an interrupt will be generated when hardware expects to receive a sof event, even if the actual sof signal is missed or corrupted. this bit is cleared when software reads the cmint register. 0: sof interrupt inactive. 1: sof interrupt active. 2rstint reset interrupt-pending flag. set by hardware when reset signaling is detected on the bus. this bit is cleared when software reads the cmint register. 0: reset interrupt inactive. 1: reset interrupt active. 1rsuint resume interrupt-pending flag. set by hardware when resume signaling is detected on the bus while usb0 is in sus- pend mode. this bit is cleared when software reads the cmint register. 0: resume interrupt inactive. 1: resume interrupt active. 0susint suspend interrupt-pending flag. when suspend detection is enabled (bit susen in register power), this bit is set by hardware when suspend signaling is detected on the bus. this bit is cleared when software reads the cmint register. 0: suspend interrupt inactive. 1: suspend interrupt active. rev. 1.1 173 c8051t620/621/320/321/322/323 usb register address = 0x07 usb register definition 23. 14. in1ie: usb0 in en dpoint interrupt enable bit76543210 name in3e in2e in1e ep0e type rrrrr/wr/wr/wr/w reset 00001111 bit name function 7:4 unused unused. read = 0000b. write = don?t care. 3in3e in endpoint 3 interrupt enable. 0: in endpoint 3 interrupt disabled. 1: in endpoint 3 interrupt enabled. 2in2e in endpoint 2 interrupt enable. 0: in endpoint 2 interrupt disabled. 1: in endpoint 2 interrupt enabled. 1in1e in endpoint 1 interrupt enable. 0: in endpoint 1 interrupt disabled. 1: in endpoint 1 interrupt enabled. 0 ep0e endpoint 0 interrupt enable. 0: endpoint 0 interrupt disabled. 1: endpoint 0 interrupt enabled. c8051t620/621/320/321/322/323 174 rev. 1.1 usb register address = 0x09 usb register definition 23. 15. out1ie: usb0 out en dpoint interrupt enable bit76543210 name out3e out2e out1e type rrrrr/wr/wr/wr reset 00001110 bit name function 7:4 unused unused. read = 0000b. write = don?t care. 3out3e out endpoint 3 interrupt enable. 0: out endpoint 3 interrupt disabled. 1: out endpoint 3 interrupt enabled. 2out2e out endpoint 2 interrupt enable. 0: out endpoint 2 interrupt disabled. 1: out endpoint 2 interrupt enabled. 1out1e out endpoint 1 interrupt enable. 0: out endpoint 1 interrupt disabled. 1: out endpoint 1 interrupt enabled. 0 unused unused. read = 0b. write = don?t care. rev. 1.1 175 c8051t620/621/320/321/322/323 usb register address = 0x0b 23.9. the serial interface engine the serial interface engine (sie) performs all low level usb protocol tasks, interrupting the processor when data has successfully been transmitted or received. when receiv ing data, the sie will interrupt the processor when a complete data packet has been received; appropriate handshaking signals are automat- ically generated by the sie. when transmitting data, the sie will interrupt the processor when a complete data packet has been transmitted and the appropriate handshake signal has been received. the sie will not interrupt the processor when corr upted/erroneous packets are received. 23.10. endpoint0 endpoint0 is managed through the usb register e0cs r (usb register definition 23.18). the index reg- ister must be loaded with 0x00 to access the e0csr register. an endpoint0 interrupt is generated when: 1. a data packet (out or setup) has been receiv ed and loaded into the endpoint0 fifo. the oprdy bit (e0csr.0) is set to 1 by hardware. 2. an in data packet has successfully been unloaded from the endpoint0 fifo and transmitted to the host; inprdy is rese t to 0 by hardware. 3. an in transaction is completed (this interrupt generated during the status stage of the transaction). 4. hardware sets the ststl bit (e0csr.2) after a c ontrol transaction ended due to a protocol violation. usb register definition 23.16. cm ie: usb0 common interrupt enable bit76543210 name sofe rstinte rsuinte susinte type rrrrr/wr/wr/wr/w reset 00000110 bit name function 7:4 unused unused. read = 0000b. write = don?t care. 3sofe start of frame interrupt enable. 0: sof interrupt disabled. 1: sof interrupt enabled. 2rstinte reset interrupt enable. 0: reset interrupt disabled. 1: reset interrupt enabled. 1rsuinte resume interrupt enable. 0: resume interrupt disabled. 1: resume interrupt enabled. 0susinte suspend interrupt enable. 0: suspend interrupt disabled. 1: suspend interrupt enabled. c8051t620/621/320/321/322/323 176 rev. 1.1 5. hardware sets the suend bit (e0csr.4) because a control transfer ended before firmware sets the dataend bit (e0csr.3). the e0cnt register (usb register definition 23.11 ) holds the number of received data bytes in the endpoint0 fifo. hardware will automatically detect protocol errors and send a stal l condition in resp onse. firmware may force a stall condition to abort the current transfer. when a stall condition is generated, the ststl bit will be set to 1 and an interrupt generated. the following conditions will cause hardware to generate a stall condition: 1. the host sends an out token during a out data phase after the dataend bit has been set to 1. 2. the host sends an in token during an in data phase after the dataend bit has been set to 1. 3. the host sends a packet that exceeds the maximum packet size for endpoint0. 4. the host sends a non-zero length data1 packet during the status phase of an in transaction. firmware sets the sdstl bit (e0csr.5) to 1. 23.10.1. endpoint0 setup transactions all control transfers must begin with a setup packet. setup packets are similar to out packets, contain- ing an 8-byte data field sent by the host. any setup packet containing a comma nd field of anything other than 8 bytes will be automatically re jected by usb0. an endpoint0 inte rrupt is generate d when the data from a setup packet is loaded into the endpoint0 fifo. software should unload the command from the endpoint0 fifo, decode the command, perform any necess ary tasks, and set the soprdy bit to indicate that it has serviced the out packet. 23.10.2. endpoint0 in transactions when a setup request is received that requires usb0 to transmit data to the host, one or more in requests will be sent by the host. for the first in tr ansaction, firmware should lo ad an in packet into the endpoint0 fifo, and set the inprdy bit (e0csr.1). an inte rrupt will be generated when an in packet is transmitted successfully. note that no interrupt will be generated if an in requ est is receiv ed before firm- ware has loaded a packet into the endpoint0 fifo . if the requested data exceeds the maximum packet size for endpoint0 (as reported to the host), the data should be split into multiple packets; each packet should be of the maximum packet size excluding the last (residual) packet. if the requested data is an inte- ger multiple of the maximum packet size for endpoint 0, the last data packet should be a zero-length packet signaling the end of the transfer. firmware should set the dataend bit to 1 after loading into the endpoint0 fifo the last data packet for a transfer. upon reception of the first in token for a particular control transfer, endpoint0 is said to be in transmit mode. in this mode, only in tokens should be sent by the host to en dpoint0. the suend bit (e0csr.4) is set to 1 if a setup or out token is receiv ed while endpoint0 is in transmit mode. endpoint0 will remain in transmit m ode until any of the following occur: 1. usb0 receives an end point0 setup or out token. 2. firmware sends a packet less than the maximum endpoint0 packet size. 3. firmware sends a zero-length packet. firmware should set the dataend bit (e0csr.3) to 1 when performing (2) and (3) above. the sie will transmit a nak in response to an in token if there is no pa cket ready in the in fifo (inprdy = 0). rev. 1.1 177 c8051t620/621/320/321/322/323 23.10.3. endpoint0 out transactions when a setup request is received that requires the host to transmit data to usb0, one or more out requests will be sent by the host. when an out packet is successfully received by usb0, hardware will set the oprdy bit (e0csr.0) to 1 and generate an endpoi nt0 interrupt. fo llowing this interrupt, firmware should unload the out packet from the endpoint 0 fifo and set the soprdy bit (e0csr.6) to 1. if the amount of data required for the transfer exceeds the maximum packet size for endpoint0, the data will be split into multiple packets. if the requested data is an integer multiple of th e maximum packet size for endpoint0 (as reported to the host), the host will send a zero-length data packet signaling the end of the transfer. upon reception of the first out token for a particular control transfer, endpoint0 is said to be in receive mode. in this mode, only out tokens should be sent by the host to endpoint0. the suend bit (e0csr.4) is set to 1 if a setup or in token is re ceived while endpoint0 is in receive mode. endpoint0 will remain in receive mode until: 1. the sie receives a setup or in token. 2. the host sends a packet less than the maximum endpoint0 packet size. 3. the host sends a zero-length packet. firmware should set the dataend bit (e0csr.3) to 1 when the expected amount of data has been received. the sie will transmit a sta ll condition if the host sends an out packet after the dataend bit has been set by firmware. an inte rrupt will be generated with the ststl bit (e0csr.2) set to 1 after the stall is transmitted. c8051t620/621/320/321/322/323 178 rev. 1.1 usb register address = 0x11 usb register definition 23.17. e0 csr: usb0 endpoint0 control bit76543210 name ssuend soprdy sdstl suend dataend ststl inprdy oprdy type r/w r/w r/w r r/w r/w r/w r reset 00000000 bit name description write read 7 ssuend serviced setup end bit. software should set this bit to 1 after servicing a setup end (bit suend) event. hardware clears the suend bit when software writes 1 to ssuend. this bit always reads 0. 6soprdy serviced oprdy bit. software should wr ite 1 to this bit after servicing a received endpoint0 packet. the oprdy bit will be cleared by a write of 1 to soprdy. this bit always reads 0. 5sdstl send stall bit. software can write 1 to this bit to terminate the current transfer (due to an error condi- tion, unexpected tr ansfer request, etc.). hardware will clear this bit to 0 when the stall handshake is transmitted. 4 suend setup end bit. hardware sets this read-only bit to 1 when a control transaction ends before software has written 1 to the dataend bit. hardware clears this bit when software writes 1 to ssuend. 3 dataend data end bit. software should write 1 to this bit: 1) when writing 1 to inprdy for the last outgoing data packet. 2) when writing 1 to inprdy for a zero-length data packet. 3) when writ- ing 1 to soprdy after servicing the last incoming data packet. this bit is automaticall y cleared by hardware. 2 ststl sent stall bit. hardware sets this bit to 1 after transmitting a stall hands hake signal. this flag must be cleared by software. 1 inprdy in packet ready bit. software should write 1 to this bit after loading a data packet into the endpoint0 fifo for transmit. hardware clears this bit and generates an interrupt under either of the fol- lowing conditions: 1) the packet is transmitted. 2) the packet is overwritten by an incoming setup packet. 3) the packet is overwritten by an incoming out packet. 0 oprdy out packet ready bit. hardware sets this read-only bit and generates an interrupt when a data packet has been received. this bit is cleared only w hen software writes 1 to the soprdy bit. rev. 1.1 179 c8051t620/621/320/321/322/323 usb register address = 0x16 23.11. configuring endpoints1-3 endpoints1-3 are configured and cont rolled through their own sets of the following control/status registers: in registers eincsrl and eincsrh, and out regi sters eoutcsrl and eoutcsrh. only one set of endpoint control/status registers is mapped into the usb register address space at a time, defined by the contents of the index register (usb register definition 23.4). endpoints1-3 can be configured as in, out, or both in/out (split mode) as described in section 23.5.1. the endpoint mode (split/normal) is selected via the split bit in register eincsrh. when split = 1, the corresponding endpoint fifo is split, and both in and out pipes are available. when split = 0, the corresponding endpoint function s as either in or out; the endpoint direction is selected by the dirsel bit in register eincsrh. endpoints1-3 can be disabled individually by the corre sponding bits in the enable register. when an end- point is disabled, it will not respond to bus traffic or stall the bus. all endpoints are enabled by default. usb register definition 23.18. e0 cnt: usb0 endpoint0 data count bit76543210 name e0cnt[6:0] type rr reset 00000000 bit name function 7 unused unused. read = 0b. write = don?t care. 6:0 e0cnt[6:0] endpoint 0 data count. this 7-bit number indicates the number of received data bytes in the endpoint 0 fifo. this number is only valid while bit oprdy is a 1. c8051t620/621/320/321/322/323 180 rev. 1.1 usb register address = 0x1e 23.12. controlling endpoints1-3 in endpoints1-3 in are managed via usb registers einc srl and eincsrh. all in endpoints can be used for interrupt, bulk, or isochronous tr ansfers. isochronous (iso) mode is enabled by writing 1 to the iso bit in register eincsrh. bulk and interrupt transfers are handled identically by hardware. an endpoint1-3 in interrupt is generated by any of the following conditions: 1. an in packet is successfully transferred to the host. 2. software writes 1 to the flush bit (eincs rl.3) when the target fifo is not empty. 3. hardware generates a stall condition. 23.12.1. endpoints1-3 in interrupt or bulk mode when the iso bit (eincsrh.6) = 0 the target endpoint operates in bulk or interrupt mode. once an end- point has been configured to operate in bulk/interrupt in mode (typically following an endpoint0 set_interface command), firmware should load an in packet into the endpoint in fifo and set the inprdy bit (eincsrl.0). upon reception of an in token, hardware will tran smit the data, clear the inprdy bit, and generate an interrupt. writing 1 to inprdy without writing any data to the endpoint fi fo will cause a zero-l ength packet to be transmitted upon reception of the next in token. usb register definition 23.19. ee nable: usb0 endpoint enable bit76543210 name een3 een2 een1 reserved type rrrrr/wr/wr/wr/w reset 11111111 bit name function 7:4 unused unused. read = 1111b. write = don?t care. 3 een3 endpoint 3 enable. this bit enables/disables endpoint 3. 0: endpoint 3 is disabled (no nack , ack, or stall on the usb network). 1: endpoint 3 is enabled (normal). 2 een2 endpoint 2 enable. this bit enables/disables endpoint 2. 0: endpoint 2 is disabled (no nack , ack, or stall on the usb network). 1: endpoint 2 is enabled (normal). 1 een1 endpoint 1 enable. this bit enables/disables endpoint 1. 0: endpoint 1 is disabled (no nack , ack, or stall on the usb network). 1: endpoint 1 is enabled (normal). 0 reserved reserved. read = 1b. must write 1b. rev. 1.1 181 c8051t620/621/320/321/322/323 a bulk or interrupt pipe can be shut down (or halted) by writing 1 to the sdstl bit (eincsrl.4). while sdstl = 1, hardware will respond to all in requests with a stall condit ion. each time hardware gener- ates a stall condition, an inte rrupt will be generated and the ststl bit (eincsrl.5) set to 1. the ststl bit must be rese t to 0 by firmware. hardware will automatically reset inprdy to 0 when a packet slot is open in the endpoin t fifo. note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the in fifo at a time. in this case, hardware will reset inprdy to 0 immedi ately after firmware loads the first packet into the fifo and sets inprdy to 1. an interr upt will not be generated in th is case; an interrupt will only be generated when a data packet is transmitted. when firmware writes 1 to the fcdt bit (eincsrh.3), the data togg le for each in packet will be toggled continuously, regardless of the handshake received from the host. this feature is typically used by inter- rupt endpoints functioning as rate feedback communi cation for isochronous endpoints. when fcdt = 0, the data toggle bit will only be toggle d when an ack is sent from the host in response to an in packet. 23.12.2. endpoints1-3 in isochronous mode when the iso bit (eincsrh.6) is set to 1, the target endpoint operates in isochronous (iso) mode. once an endpoint has been configured fo r iso in mode, the host will send one in token (dat a request) per frame; the location of data within each frame may vary. because of this, it is recommended that double buffering be enabled for iso in endpoints. hardware will automatically reset inpr dy (eincsrl.0) to 0 when a packet slot is open in the endpoint fifo. note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the in fifo at a time . in this case, hardware will reset inprdy to 0 imme diately after firm- ware loads the first packet into the fifo and sets inprdy to 1. an in terrupt will not be generated in this case; an interrupt will only be generated when a data packet is transmitted. if there is not a data packet ready in the endpoint fifo when usb0 receives an in token from the host, usb0 will transmit a zero-length data packet and set the undrun bit (eincsrl.2) to 1. the iso update feature (see section 23.7) can be useful in starting a double buffered iso in endpoint. if the host has already set up the iso in pipe (has b egun transmitting in tokens) when firmware writes the first data packet to the endpoint fifo, the next in to ken may arrive and the first data packet sent before firmware has written the second (double buffered ) data packet to the fifo. the iso update feature ensures that any data packet written to the endpoint fifo will not be tran smitted during the current frame; the packet will only be sent after a sof signal has been received. c8051t620/621/320/321/322/323 182 rev. 1.1 usb register address = 0x11 usb register definition 23.20. eincsrl: usb0 in endpoint control low bit76543210 name clrdt ststl sdstl flush undrun fifone inprdy type r w r/w r/w r/w r/w r/w r/w reset 00000000 bit name description write read 7 unused unused. read = 0b. write = don?t care. 6 clrdt clear data toggle bit. software should write 1 to this bit to reset the in end- point data toggle to 0. this bit always reads 0. 5ststl sent stall bit. hardware sets this bit to 1 when a stall ha ndshake signal is transmitted. the fifo is flushed, and the inprdy bit cleared. th is flag must be cleared by software. 4sdstl send stall. software should write 1 to this bit to generate a stall handshake in response to an in token. software should write 0 to this bit to te rminate the stall signal. this bit has no effect in iso mode. 3flush fifo flush bit. writing a 1 to this bit flushes the next packe t to be transmitted from the in endpoint fifo. the fifo pointer is reset and the inprdy bit is cleared. if the fifo contains mul- tiple packets, software must write 1 to flush for each packet. hardware resets the flush bit to 0 when the fifo flush is complete. 2 undrun data underrun bit. the function of this bit depends on the in endpoint mode: iso: set when a zero-length packet is sent after an in token is received while bit inprdy = 0. interrupt/bulk: set when a nak is re turned in response to an in token. this bit must be cleared by software. 1fifone fifo not empty. 0: the in endpoint fifo is empty. 1. the in endpoint fifo contains one or more packets. 0 inprdy in packet ready. software should write 1 to this bit after load ing a data packet into the in endpoint fifo. hardware clears inprdy due to any of the following: 1) a data packet is transmitted. 2) double buffering is enabled (dbien = 1) and there is an open fifo packet slot. 3) if the endpoint is in isochronous mode (iso = 1) and isoud = 1, inprdy will read 0 until the next sof is received. note: an interrupt (if enabled) will be generated when hardware clears inprdy as a result of a packet being transmitted. rev. 1.1 183 c8051t620/621/320/321/322/323 usb register address = 0x12 23.13. controlling endpoints1-3 out endpoints1-3 out are managed via usb registers eoutcsrl and eoutcsrh. all out endpoints can be used for interrupt, bulk, or isochronous transfers. isochronous (iso) mode is enabled by writing 1 to the iso bit in register eoutcsrh. bu lk and interrupt transfers are handled identically by hardware. an endpoint1-3 out interrupt may be generated by the following: 1. hardware sets the oprd y bit (eincsrl.0) to 1. 2. hardware generates a stall condition. usb register definition 23.21. eincsrh: usb0 in endpoint control high bit76543210 name dbien iso dirsel fcdt split type r/w r/w r/w r r/w r/w r r reset 00000000 bit name function 7dbien in endpoint double-buffer enable. 0: double-buffering disabled for the selected in endpoint. 1: double-buffering enabled for the selected in endpoint. 6iso isochronous transfer enable. this bit enables/disables isochronous transfers on the current endpoint. 0: endpoint configured for bulk/interrupt transfers. 1: endpoint configured for isochronous transfers. 5 dirsel endpoint direction select. this bit is valid only when the sele cted fifo is not split (split = 0). 0: endpoint direction selected as out. 1: endpoint direction selected as in. 4 unused unused. read = 0b. write = don?t care. 3fcdt force data toggle bit. 0: endpoint data toggle switches only wh en an ack is received following a data packet transmission. 1: endpoint data toggle forced to switch after every data packet is transmitted, regard- less of ack reception. 2 split fifo split enable. when split = 1, the selected endpoint fifo is split. the upper half of the selected fifo is used by the in endpoint; the lower half of the selected fifo is used by the out endpoint. 1:0 unused unused. read = 00b. write = don?t care. c8051t620/621/320/321/322/323 184 rev. 1.1 23.13.1. endpoints1-3 out interrupt or bulk mode when the iso bit (eoutcsrh.6) = 0 the target endpoint operates in bulk or interrupt mode. once an end- point has been configured to operate in bulk/interrupt out mode (typically following an endpoint0 set_interface command), hardware will set the oprdy bit (eoutcsrl.0) to 1 and generate an interrupt upon reception of an out token and data packet. the number of bytes in the current out data packet (the packet ready to be unloaded from the fifo) is given in the eoutcnth and eoutcntl reg- isters. in response to this interrup t, firmware should unload the data packet from the out fifo and reset the oprdy bit to 0. a bulk or interrupt pipe can be shut down (or halt ed) by writing 1 to the sdstl bit (eoutcsrl.5). while sdstl = 1, hardware will respond to all out requests with a stall condition. each time har dware gener- ates a stall condition, an interrupt will be generat ed and the ststl bit (eoutcsrl.6) set to 1. the ststl bit must be rese t to 0 by firmware. hardware will automatically set oprdy when a packet is ready in the out fifo. note that if double buff- ering is enabled for the target endpoint, it is possible for two packets to be ready in the out fifo at a time. in this case, hardware will set oprdy to 1 immediatel y after firmware unloads t he first packet and resets oprdy to 0. a second interrupt will be gener ated in this case. 23.13.2. endpoints1-3 out isochronous mode when the iso bit (eoutcsrh.6) is set to 1, the ta rget endpoint operates in isochronous (iso) mode. once an endpoint has been config ured for iso out mode, the host will send exactly one data per usb frame; the location of the data packet within each frame may vary, however. because of this, it is recom- mended that double buffering be enabled for iso out endpoints. each time a data packet is received, hardware will l oad the received data packe t into the endpoint fifo, set the oprdy bit (eoutcsrl.0) to 1, and generate an interrupt (if enabled). firmware would typically use this interrupt to unload the data packet from the endpoint fifo and reset the oprdy bit to 0. if a data packet is received when there is no room in the endpoint fifo, an inte rrupt will be generated and the ovrun bit (eoutcsrl.2) set to 1. if usb0 rece ives an iso data packet with a crc error, the data packet will be loaded into the endpoint fifo, oprdy will be set to 1, an interrupt (if enabled) will be gen- erated, and the dataerr bit (eoutcsrl.3) will be se t to 1. software should check the dataerr bit each time a data packet is unloaded from an iso out endpoint fifo. rev. 1.1 185 c8051t620/621/320/321/322/323 usb register address = 0x14 usb register definition 23. 22. eoutcsrl: usb0 out en dpoint control low byte bit76543210 name clrdt ststl sdstl flush daterr ovrun fifoful oprdy type w r/w r/w r/w r r/w r r/w reset 00000000 bit name description write read 7 clrdt clear data toggle bit. software should write 1 to this bit to reset the out end- point data toggle to 0. this bit always reads 0. 6ststl sent stall bit. hardware sets this bit to 1 when a stall ha ndshake signal is transmitted. this flag must be cleared by software. 5sdstl send stall bit. software should write 1 to this bit to generate a stall handshake. software should write 0 to this bit to terminate the stall signal. this bit has no effect in iso mode. 4flush fifo flush bit. writing a 1 to this bit flushes the next pa cket to be read from the out endpoint fifo. the fifo pointer is reset and the oprdy bi t is cleared. multip le packets must be flushed individually. hardware resets the fl ush bit to 0 when the flush is complete. note: if data for the current packet has already been read from the fifo, the flush bit should not be used to flush the packet. instead, the fifo should be read manually. 3daterr data error bit. in iso mode, this bit is set by hardware if a received packet has a crc or bit-stuffing error. it is cleared when software clears oprdy. this bit is only valid in iso mode. 2 ovrun data overrun bit. this bit is set by hardware when an incoming data packet cannot be loaded into the out endpoint fifo. this bit is only valid in iso mode, and must be cleared by software. 0: no data overrun. 1: a data packet was lost because of a fu ll fifo since this flag was last cleared. 1 fifoful out fifo full. this bit indicates the contents of the out fifo. if double buffering is enabled (dbien = 1), the fifo is full when the fi fo contains two packets. if dbien = 0, the fifo is full when the fifo contains one packet. 0: out endpoint fifo is not full. 1: out endpoint fifo is full. 0oprdy out packet ready. hardware sets this bit to 1 and generates an interrupt when a data packet is available. software should clear this bit after each data packet is unloaded from the out endpoint fifo. c8051t620/621/320/321/322/323 186 rev. 1.1 usb register address = 0x15 usb register address = 0x16 usb register definition 23.23. eoutcs rh: usb0 out endp oint control high byte bit76543210 name dboen iso type r/wr/wrrrrrr reset 00000000 bit name function 7dboen double-buffer enable. 0: double-buffering disabled for the selected out endpoint. 1: double-buffering enabled for the selected out endpoint. 6iso isochronous transfer enable. this bit enables/disables isochronous transfers on the current endpoint. 0: endpoint configured for bulk/interrupt transfers. 1: endpoint configured for isochronous transfers. 5:0 unused unused. read = 000000b. write = don?t care. usb register definition 23.24. eout cntl: usb0 out endpoint count low bit76543210 name eocl[7:0] type r reset 00000000 bit name function 7:0 eocl[7:0] out endpoint count low byte. eocl holds the lower 8-bits of the 10-bit nu mber of data bytes in the last received packet in the current out endpoint fifo. th is number is only valid while oprdy = 1. rev. 1.1 187 c8051t620/621/320/321/322/323 usb register address = 0x17 usb register definition 23.25. eoutcnth: usb0 ou t endpoint count high bit76543210 name eoch[1:0] type rrrrrrrr reset 00000000 bit name function 7:2 unused unused. read = 000000b. write = don?t care. 1:0 eoch[1:0] out endpoint count high byte. eoch holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in the current out endpoint fifo. th is number is only valid while oprdy = 1. c8051t620/621/320/321/322/323 188 rev. 1.1 24. smbus the smbus i/o interface is a two-wire, bi-directional serial bus. the smbus is compliant with the system management bus specification, version 1.1, and compatible with the i 2 c serial bus. reads and writes to the interface by the system contro ller are byte oriented with the smbu s interface autonom ously controlling the serial transfer of the data. data can be transferre d at up to 1/20th of the system clock as a master or slave (this can be faster than allowed by the smbus specification, depending on the system clock used). a method of extending the clock-low duration is ava ilable to accommodate devices with different speed capabilities on the same bus. the smbus interface may operate as a master and/or slave, and may function on a bus with multiple mas- ters. the smbus provides control of sda (serial data), scl (serial clock) generation and synchronization, arbitration logic, and start/stop control and genera tion. the smbus peripheral can be fully driven by software (i.e., software ac cepts/rejects slave addresses, and generat es acks), or hardware slave address recognition and automatic ack generation can be enabled to minimize software overhead. a block dia- gram of the smbus peripheral and the associated sfrs is shown in figure 24.1. figure 24.1. smbus block diagram data path control smbus control logic c r o s s b a r scl filter n sda control scl control interrupt request port i/o smb0cn s t a a c k r q a r b l o s t a c k s i t x m o d e m a s t e r s t o 01 00 10 11 t0 overflow t1 overflow tmr2h overflow tmr2l overflow smb0cf e n s m b i n h b u s y e x t h o l d s m b t o e s m b f t e s m b c s 1 s m b c s 0 0 1 2 3 4 5 6 7 smb0dat sda filter n smb0adr s l v 4 s l v 2 s l v 1 s l v 0 g c s l v 5 s l v 6 s l v 3 smb0adm s l v m 4 s l v m 2 s l v m 1 s l v m 0 e h a c k s l v m 5 s l v m 6 s l v m 3 arbitration scl synchronization hardware ack generation scl generation (master mode) sda control hardware slave address recognition irq generation rev. 1.1 189 c8051t620/621/320/321/322/323 24.1. supporting documents it is assumed the reader is fam iliar with or has access to th e following supporting documents: 1. the i 2 c-bus and how to use it (including s pecifications), philips semiconductor. 2. the i 2 c-bus specification?version 2.0, philips semiconductor. 3. system management bus specification? version 1.1, sbs implementers forum. 24.2. smbus configuration figure 24.2 shows a typical smbus configuration. th e smbus specification allows any recessive voltage between 3.0 v and 5.0 v; different devices on the bus ma y operate at different voltage levels. the bi-direc- tional scl (serial clock) and sda (serial data) lines mu st be connected to a positive power supply voltage through a pullup resistor or similar circuit. every devi ce connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessive state) when the bus is free. the maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. figure 24.2. typical smbus configuration 24.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addres sed slave transmitter to a master receiver (read). the master device initiates both types of data transfer s and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitr ation. note that it is not necessary to specify one device as the master in a system ; any device who transmits a star t and a slave address becomes the master for the duration of that transfer. a typical smbus transaction consists of a start cond ition followed by an address byte (bits7?1: 7-bit slave address; bit0: r/w direction bit), one or more bytes of data, and a stop condition. bytes that are received (by a master or slave) are acknowledg ed (ack) with a low sda during a high scl (see figure 24.3). if the receiving devi ce does not ack, the tr ansmitting device will read a nack (not acknowl- edge), which is a high sda during a high scl. the direction bit (r/w) occupies the least-significant bit position of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. vdd = 5v master device slave device 1 slave device 2 vdd = 3v vdd = 5v vdd = 3v sda scl c8051t620/621/320/321/322/323 190 rev. 1.1 all transactions are initiated by a master, with one or more addressed slave devices as the target. the master generates the start condition and then transmit s the slave address and dire ction bit. if the trans- action is a write operation from the master to the slave, the master tr ansmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operations , the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to term inate the transaction and free the bu s. figure 24.3 illustrates a typical smbus transaction. figure 24.3. smbus transaction 24.3.1. transmitter vs. receiver on the smbus communications interface, a device is the ?transmitter? when it is sending an address or data byte to another device on the bus. a device is a ?receiver? when an ad dress or data byte is being sent to it from another device on the bus. the transmitter controls the sda line during the address or data byte. after each byte of address or data information is sent by the transmitter, the receiver sends an ack or nack bit during the ack phase of the transfer, dur ing which time the receiver controls the sda line. 24.3.2. arbitration a master may start a transfer only if the bus is free. th e bus is free after a stop condition or after the scl and sda lines remain high for a specified time (see section ?24.3.5. scl high (smbus free) timeout? on page 191). in the event that two or more devices attempt to begin a transfer at the same time, an arbitra- tion scheme is employed to force one master to give up the bus. the master devices continue transmitting until one attempts a high while the other transmits a low. since the bus is open-drain, the bus will be pulled low. the master attempting th e high will detect a low sda and lo se the arbitration. the winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. this arbitration scheme is non-destru ctive: one device always wins, and no data is lost. 24.3.3. clock low extension smbus provides a clock synchronizati on mechanism, similar to i2c, wh ich allows devices with different speed capabilities to coexist on the bus. a clock-low extension is used du ring a transfer in order to allow slower slave devices to communica te with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. 24.3.4. scl low timeout if the scl line is held low by a slave device on the bus, no further communication is possible. furthermore, the master cannot force the scl line high to correct th e error condition. to solve this problem, the smbus protocol specifies that devices participating in a tran sfer must detect any clock cy cle held low longer than 25 ms as a ?timeout? condition. devices that have detected the timeout conditi on must reset the communi- cation no later than 10 ms after detecting the timeout condition. when the smbtoe bit in smb0cf is set, timer 3 is used to detect scl low timeouts. timer 3 is forced to reload when scl is high, and allowed to count when sc l is low. with timer 3 enabled and configured to sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop rev. 1.1 191 c8051t620/621/320/321/322/323 overflow after 25 ms (and smbtoe set), the timer 3 interrupt service routine can be used to reset (disable and re-enable) the smbus in the event of an scl low timeout. 24.3.5. scl high (smbus free) timeout the smbus specification stipulates th at if the scl and sda lines remain high for more that 50 s, the bus is designated as free. when the sm bfte bit in smb0cf is set, the bu s will be considered free if scl and sda remain high for more than 10 smbus clock source periods (as defined by the timer configured for the smbus clock source). if the smbus is waiting to generate a master start, the start will be generated following this timeout. a clock source is required for free timeout detection, even in a slave-only implemen- tation. 24.4. using the smbus the smbus can operate in both master and slave modes. the interface provides timing and shifting con- trol for serial transfers; higher level protocol is dete rmined by user software. the smbus interface provides the following application-independent features: ? byte-wise serial data transfers ? clock signal generation on scl (master mode only) and sda data synchronization ? timeout/bus error recognition, as defined by the smb0cf configuration register ? start/stop timing, detection, and generation ? bus arbitration ? interrupt generation ? status information ? optional hardware recognition of slave address and automatic acknowledgement of address/data smbus interrupts are generated for each data byte or slave address that is transferred. when hardware acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hard- ware is acting as a data transmitter or receiver. wh en a transmitter (i.e., sending address/data, receiving an ack), this interrupt is generated after the ack cycl e so that software may read the received ack value; when receiving data (i.e., receiving address/data, send ing an ack), this interrupt is generated before the ack cycle so that software may def ine the outgoing ack value. if har dware acknowledgement is enabled, these interrupts are always generated after the ack cycle. see section 24.5 for more details on transmis- sion sequences. interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected) . software should read the smb0cn (smbus control register) to find the cause of the smbus interrupt. th e smb0cn register is described in section 24.4.2; table 24.5 provides a quick smb0cn decoding reference. 24.4.1. smbus conf iguration register the smbus configuration register (s mb0cf) is used to enable the smbus master and/or slave modes, select the smbus clock source, and select the smbus timing and timeout options . when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhibited, the smbus in terface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will not generate any slave inte rrupts. when the inh bit is set, all slave events will be inhibited following the ne xt start (interrupts will cont inue for the duration of the current transfer). c8051t620/621/320/321/322/323 192 rev. 1.1 the smbcs1?0 bits select the smbus clock source, which is used only when operating as a master or when the free timeout detection is enabled. when op erating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 24.1. note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. for example, timer 1 overflows may generate the smbus and uart baud rates simultaneously. timer configuration is covered in section ?28. timers? on page 240. equation 24.1. minimum scl high and low times the selected clock source should be configured to establish the minimum scl high and low times as per equation 24.1. when the interface is operating as a master (and scl is not driven or extended by any other devices on the bus), the typical smbus bit rate is approximated by equation 24.2. equation 24.2. typical smbus bit rate figure 24.4 shows the typical scl generation described by equation 24.2. notice that t high is typically twice as large as t low . the actual scl output may vary due to other devices on the bus (scl may be extended low by slower slave devices, or driven low by contending master devices). the bit rate when operating as a master will neve r exceed the limits defined by equation equation 24.1. figure 24.4. typical smbus scl generation table 24.1. smbus clock source selection smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow t highmin t lowmin 1 f clocksourceoverflow ---------------------------------- ----------- - == bitrate f clocksourceoverflow 3 --------------- ------------------------------ - = scl timer source overflows scl high timeout t low t high rev. 1.1 193 c8051t620/621/320/321/322/323 setting the exthold bit extends the minimum setup and hold times for the sda line. the minimum sda setup time defines the absolute mini mum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that the current sda value remains stable after scl transitions from high-to-low. exthold should be set so that the minimum setup and hold times meet the smbus specification requirements of 250 ns and 300 ns, respectively. table 24.2 shows the min- imum setup and hold times for the two exthold settings. setup and hold time extensions are typically necessary when sysclk is above 10 mhz. with the smbtoe bit set, timer 3 should be configured to overflow after 25 ms in order to detect scl low timeouts (see section ?24. 3.4. scl low timeout? on page 190). th e smbus interface will force timer 3 to reload while scl is high, and allow timer 3 to count wh en scl is low. the timer 3 interrupt service routine should be used to reset smbus communication by disabling and re-enabling the smbus. smbus free timeout detection can be enabled by setting the smbfte bit. when this bit is set, the bus will be considered free if sda and scl remain high for more than 10 smbus clock source periods (see figure 24.4). table 24.2. minimum sda setup and hold times exthold minimum sda setup time minimum sda hold time 0 t low ? 4 system clocks or 1 system clock + s/w delay * 3 system clocks 1 11 system clocks 12 system clocks note: setup time for ack bit transmissions and the msb of all data transfers. when using software acknowledgement, the s/w delay occurs between the time smb0dat or ack is written and when si is cleared. note that if si is cleared in the same write that defines the outgoing ack value, s/w delay is zero. c8051t620/621/320/321/322/323 194 rev. 1.1 sfr address = 0xc1 sfr definition 24.1. smb0cf: smbus clock/configuration bit76543210 name ensmb inh busy exthold smbtoe smbfte smbcs[1:0] type r/w r/w r r/w r/w r/w r/w reset 00000000 bit name function 7ensmb smbus enable. this bit enables the smbus interface when set to 1. when enabled, the interface constantly monitors the sda and scl pins. 6inh smbus slave inhibit. when this bit is set to logic 1, the smbu s does not generate an interrupt when slave events occur. this effectively removes the smbus slave from the bus. master mode interrupts are not affected. 5busy smbus busy indicator. this bit is set to logic 1 by hardware when a transfer is in progress. it is cleared to logic 0 when a stop or free-timeout is sensed. 4 exthold smbus setup and hold time extension enable. this bit controls the sda setup and hold times according to table 24.2. 0: sda extended setup and hold times disabled. 1: sda extended setup and hold times enabled. 3smbtoe smbus scl timeout detection enable. this bit enables scl low timeout detectio n. if set to logic 1, the smbus forces timer 3 to reload while scl is high and allows timer 3 to count when scl goes low. if timer 3 is configured to split mode, only t he high byte of the timer is held in reload while scl is high. timer 3 should be programmed to generate interrupts at 25 ms, and the timer 3 interrupt service routine should reset smbus communication. 2smbfte smbus free timeout detection enable. when this bit is set to logic 1, the bus will be considered free if scl and sda remain high for more than 10 sm bus clock source periods. 1:0 smbcs[1:0] smbus clock source selection. these two bits select the smbus clock sour ce, which is used to generate the smbus bit rate. the selected device should be configured according to equation 24.1. 00: timer 0 overflow 01: timer 1 overflow 10: timer 2 high byte overflow 11: timer 2 low byte overflow rev. 1.1 195 c8051t620/621/320/321/322/323 24.4.2. smb0cn control register smb0cn is used to control the interface and to provid e status information (see sfr definition 24.2). the higher four bits of smb0cn (master, txmode, sta, and sto) form a status vector that can be used to jump to service routines. master indicates whether a device is the master or slave during the current transfer. txmode indicates whether the device is tr ansmitting or receiving data for the current byte. sta and sto indicate that a start and/or stop ha s been detected or generated since the last smbus interrupt. sta and sto are also used to generate start and stop conditions when operating as a mas- ter. writing a 1 to sta will cause the smbus interface to enter master mode and generate a start when the bus becomes free (sta is not cleared by hardwar e after the start is generated). writing a 1 to sto while in master mode will cause the interface to generate a stop and end the current transfer after the next ack cycle. if sto and sta are both set (while in master mode), a stop followed by a start will be generated. the arblost bit indicates that the interface has lost an arbitration. this may occur anytime the interface is transmitting (master or slave). a lost arbitration while operating as a slave indicates a bus error condi- tion. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see table 24.3 for more details. important note about the si bit: the smbus interface is stalled while si is set; thus scl is held low, and the bus is stalled until software clears si. 24.4.2.1. software ack generation when the ehack bit in register smb0 adm is cleared to 0, the firmware on the device must detect incom- ing slave addresses and ack or nack the slave addres s and incoming data bytes. as a receiver, writing the ack bit defines the outgoing ack value; as a transmitter, reading the ack bit indicates the value received during the last ack cycle. ackrq is set each ti me a byte is received, indi cating that an outgoing ack value is needed. when ackrq is set, software should write the desired outgoing value to the ack bit before clearing si. a nack will be g enerated if software does not write the ack bit before clearing si. sda will reflect the defined ack value immediately following a write to the ack bit; however scl will remain low until si is cleared. if a received slave address is not acknowledged, further slave events will be ignored until the next start is detected. 24.4.2.2. hardwa re ack generation when the ehack bit in register smb0adm is set to 1, automatic slave address recognition and ack gen- eration is enabled. more detail about automatic slave address recognition can be found in section 24.4.3. as a receiver, the value currently specified by the ac k bit will be automatically sent on the bus during the ack cycle of an incoming data byte. as a transmitter, reading the ack bit indicates the value received on the last ack cycle. the ackrq bit is not used when hardware ack generation is enabled. if a received slave address is nacked by hardware, further sl ave events will be ignored un til the next start is detected, and no interrupt will be generated. table 24.3 lists all sources for hardware changes to the smb0cn bits. refer to table 24.5 for smbus sta- tus decoding using the smb0cn register. c8051t620/621/320/321/322/323 196 rev. 1.1 sfr address = 0xc0; bit-addressable sfr definition 24.2. sm b0cn: smbus control bit76543210 name master txmode sta sto ackrq arblost ack si type rrr/wr/wrrr/wr/w reset 00000000 bit name description read write 7 master smbus master/slave indicator. this read-only bit indicates when the smbus is operating as a master. 0: smbus operating in slave mode. 1: smbus operating in master mode. n/a 6txmode smbus transmit mode indicator. this read-only bit indicates when the smbus is operating as a transmitter. 0: smbus in receiver mode. 1: smbus in transmitter mode. n/a 5sta smbus start flag. 0: no start or repeated start detected. 1: start or repeated start detected. 0: no start generated. 1: when configured as a master, initiates a start or repeated start. 4sto smbus stop flag. 0: no stop condition detected. 1: stop condition detected (if in slave mode) or pend- ing (if in master mode). 0: no stop condition is transmitted. 1: when configured as a master, causes a stop condition to be transmit- ted after the next ack cycle. cleared by hardware. 3ackrq smbus acknowledge request. 0: no ack requested 1: ack requested n/a 2arblost smbus arbitration lost indicator. 0: no arbitration error. 1: arbitration lost n/a 1ack smbus acknowledge. 0: nack received. 1: ack received. 0: send nack 1: send ack 0si smbus interrupt flag. this bit is set by hardware under the conditions listed in table 15.3. si must be cleared by software. while si is set, scl is held low and the smbus is stalled. 0: no interrupt pending 1 : interrupt pending 0: clear interrupt, and initi- ate next state machine event. 1: force interrupt. rev. 1.1 197 c8051t620/621/320/321/322/323 24.4.3. hardware slave address recognition the smbus hardware has the capability to automatically recognize incoming slav e addresses and send an ack without software intervention. automatic slave address recognition is enabled by setting the ehack bit in register smb0adm to 1. this will enable both automatic slave address recognition and automatic hardware ack generation for received bytes (as a mast er or slave). more detail on automatic hardware ack generation can be found in section 24.4.2.2. the registers used to define which address(es) ar e recognized by the hardware are the smbus slave address register (sfr definition 24.3) and the smbus slave address mask register (sfr definition 24.4). a single address or range of addresses (including the general call address 0x00) can be specified using these two registers. the most-significant seven bits of the two registers are used to define which addresses will be acked. a 1 in bit pos itions of the slave address mask slvm[6:0] enable a comparison between the received slave address and the hardware?s sl ave address slv[6:0] for those bits. a 0 in a bit of the slave address mask means th at bit will be treated as a ?don?t care? for comparison purposes. table 24.3. sources for hardware changes to smb0cn bit set by hardware when: cleared by hardware when: master ? a start is generated. ? a stop is generated. ? arbitration is lost. txmode ? start is generated. ? smb0dat is written before the start of an smbus frame. ? a start is detected. ? arbitration is lost. ? smb0dat is not written before the start of an smbus frame. sta ? a start followed by an address byte is received. ? must be cleared by software. sto ? a stop is detected while addressed as a slave. ? arbitration is lost due to a detected stop. ? a pending stop is generated. ackrq ? a byte has been received and an ack response value is needed (only when hardware ack is not enabled). ? after each ack cycle. arblost ? a repeated start is detected as a master when sta is low (unwanted repeated start). ? scl is sensed low while attempting to generate a stop or repeated start condition. ? sda is sensed low while transmitting a 1 (excluding ack bits). ? each time si is cleared. ack ? the incoming ack value is low (acknowledge). ? the incoming ack value is high (not acknowledge). si ? a start has been generated. ? lost arbitration. ? a byte has been transmitted and an ack/nack received. ? a byte has been received. ? a start or repeated start followed by a slave address + r/w has been received. ? a stop has been received. ? must be cleared by software. c8051t620/621/320/321/322/323 198 rev. 1.1 in this case, either a 1 or a 0 value are acceptable on the incoming slave address. a dditionally, if the gc bit in register smb0adr is set to 1, hardware will reco gnize the general call addr ess (0x00). table 24.4 shows some example parame ter settings and the slave addresses t hat will be recognized by hardware under those conditions. sfr address = 0xc7 table 24.4. hardware address recognition examples (ehack = 1) hardware slave address slv[6:0] slave address mask slvm[6:0] gc bit slave addresses recognized by hardware 0x34 0x7f 0 0x34 0x34 0x7f 1 0x34, 0x00 (general call) 0x34 0x7e 0 0x34, 0x35 0x34 0x7e 1 0x34, 0x35, 0x00 (general call) 0x70 0x73 0 0x70, 0x74, 0x78, 0x7c sfr definition 24.3. smb0 adr: smbus slave address bit76543210 name slv[6:0] gc type r/w r/w reset 00000000 bit name function 7:1 slv[6:0] smbus hardware slave address. defines the smbus slave address(es) for automatic hardware acknowledgement. only address bits which have a 1 in the corresponding bit position in slvm[6:0] are checked against the incoming address. this allows multiple addresses to be recognized. 0gc general call address enable. when hardware address reco gnition is enabled (ehack = 1), this bit will deter- mine whether the general call address (0 x00) is also recognized by hardware. 0: general call ad dress is ignored. 1: general call address is recognized. rev. 1.1 199 c8051t620/621/320/321/322/323 sfr address = 0xcf sfr definition 24.4. smb0ad m: smbus slave address mask bit76543210 name slvm[6:0] ehack type r/w r/w reset 11111110 bit name function 7:1 slvm[6:0] smbus slave address mask. defines which bits of register smb0adr are compared with an incoming address byte, and which bits are ignored. any bit set to 1 in slvm[6:0] enables compari- sons with the corresponding bit in slv[6:0]. bits set to 0 are ignored (can be either 0 or 1 in the incoming address). 0ehack hardware acknowledge enable. enables hardware acknowledgement of slave address and received data bytes. 0: firmware must manually acknowledge all incoming address and data bytes. 1: automatic slave address recognition and hardware acknowledge is enabled. c8051t620/621/320/321/322/323 200 rev. 1.1 24.4.4. data register the smbus data register smb0dat holds a byte of serial data to be transmitted or one that has just been received. software may safely read or write to the data register when the si flag is set. software should not attempt to access the smb0dat register when the smbus is enabled and the si flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. data in smb0dat is always shifted ou t msb first. after a byte has been received, the first bit of received data is located at the msb of smb0dat. while data is being shifted out, data on the bus is simultaneously being shifted in. smb0dat always contains the last data byte present on the bus. in the event of lost arbi- tration, the transition from master transmitter to slave receiver is made with the correct data or address in smb0dat. sfr address = 0xc2 sfr definition 24.5. smb0dat: smbus data bit76543210 name smb0dat[7:0] type r/w reset 00000000 bit name function 7:0 smb0dat[7:0] smbus data. the smb0dat register contains a byte of data to be transmitted on the smbus serial interface or a byte that has just b een received on the smbus serial interface. the cpu can read from or write to this regi ster whenever the si serial interrupt flag (smb0cn.0) is set to logic 1. the serial data in the register remains stable as long as the si flag is set. when the si flag is not set, the system may be in the process of shifting data in/out and the cpu shou ld not attempt to access this register. rev. 1.1 201 c8051t620/621/320/321/322/323 24.5. smbus transfer modes the smbus interface may be configured to operate as master and/or slave. at any particular time, it will be operating in one of the following four modes: master transmitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mo de any time a start is generated, and remains in master mode until it loses an arbitration or generates a stop. an smbus interrupt is generated at the end of all smbus byte frames. note that the position of the ack interrupt when operating as a receiver depends on whether hardware ack generation is enabled . as a receiver, the inte rrupt for an ack occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack genera- tion is enabled. as a transmitter, interrupts occur after the ack, regardless of whether hardware ack gen- eration is enabled or not. 24.5.1. write se quence (master) during a write sequence, an smbus master writes data to a slave device. the master in this transfer will be a transmitter during the address byte, and a transmitter during all data bytes. the smbus interface gener- ates the start condition and transmits the first byte containing the address of the target slave and the data direction bit. in this case the data direction bi t (r/w) will be logic 0 (write). the master then trans- mits one or more bytes of serial data. after each byte is transmitted, an acknowledge bit is generated by the slave. the transfer is ended wh en the sto bit is set and a stop is generated. note that the interface will switch to master receiver mode if smb0dat is not written following a master transm itter interrupt. figure 24.5 shows a typical master write sequence. two transmit data bytes are shown, though any num- ber of bytes may be transmitted. notice that all of the ?data byte transferred? interrupts occur after the ack cycle in this mode, regardless of whether hardware ack generation is enabled. figure 24.5. typical master write sequence a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) c8051t620/621/320/321/322/323 202 rev. 1.1 24.5.2. read sequence (master) during a read sequence, an smbus ma ster reads data from a slave devic e. the master in this transfer will be a transmitter during the address byte, and a receiv er during all data bytes. the smbus interface gener- ates the start condition and transmits the first byte containing the address of the target slave and the data direction bit. in this case the data direction bit (r/w) will be lo gic 1 (read). serial data is then received from the slave on sda while the smbus outputs the serial clock. the slave transmits one or more bytes of serial data. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received byte. software must writ e the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardware will autom atically generate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. writing a 1 to the ack bit generates an ack; writing a 0 generates a nack. software should write a 0 to the ack bit for the last data transfer, to transmit a nack. the interface exits master receiver mode after the sto bit is set and a stop is generated. the interface will switch to master transmitter mode if smb0dat is written while an active master receiver. figure 24.6 shows a typical master read sequence. two received data bytes are shown, though any number of bytes may be received. notice that the ?data byte transferred? interrupts occur at different places in the sequence, depending on whether hardware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. figure 24.6. typical master read sequence data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) rev. 1.1 203 c8051t620/621/320/321/322/323 24.5.3. write sequence (slave) during a write sequence, an smbus ma ster writes data to a slave device. the slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode when a start followed by a slave address and direc- tion bit (write in this case) is received. if hardware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ac krq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generation is enabled, the hardware will apply the ac k for a slave address which matches the criteria set up by smb0adr and smb0adm. the inte rrupt will occur after the ack cycle. if the received slave address is ignore d (by software or hardware), slav e interrupts will be inhibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are received. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received byte. software must writ e the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardware will autom atically generate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. the interface exits slave re ceiver mode after receiving a stop. note that the interface will switch to slave transmitter mode if smb0da t is written while an active slave receiv er. figure 24.7 shows a typical slave write sequence. two received data bytes are shown, though any number of bytes may be received. notice that the ?data byte transferred? interrupts occur at different places in the sequence, depending on whether hardware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. figure 24.7. typical slave write sequence p w sla s data byte data byte a a a s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) c8051t620/621/320/321/322/323 204 rev. 1.1 24.5.4. read se quence (slave) during a read sequence, an smbus ma ster reads data from a slave device. the slave in this transfer will be a receiver during the address byte, and a transm itter during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode (to receive the slave address) when a start followed by a slave address and direction bit (read in this case) is received. if hardware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generat ion is enabled, the hardware will apply the ack for a slave address which matches the criteria set up by smb0adr and smb0adm. the interrupt will occur after the ack cycle. if the received slave address is ignore d (by software or hardware), slav e interrupts will be inhibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are trans- mitted. if the received slave address is acknowledged, data should be written to smb0dat to be transmit- ted. the interface enters slave transmitter mode, and transmits one or more bytes of data. after each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ack, smb0dat should be written with the next data byte. if the acknowle dge bit is a nack, smb0dat should not be written to before si is cleared (an error condition may be gen erated if smb0dat is wr itten following a received nack while in slave transmitter mode ). the interface exits slave transmitter mode after receiving a stop. note that the interface will switch to slave receiver mode if smb0da t is not written following a slave transmitter interrupt. figure 24.8 shows a typical slave read sequence. two transmitted data bytes are shown, though any number of bytes may be transmitted. notice that all of the ?data byte transferred? inter- rupts occur after the ack cycle in this mode, regardless of whether hardware ack generation is enabled. figure 24.8. typical slave read sequence 24.6. smbus status decoding the current smbus status can be easily decoded usin g the smb0cn register. the appropriate actions to take in response to an smbus event depend on whether hardware slave address recognition and ack generation is enabled or disabled. table 24.5 descri bes the typical actions when hardware slave address recognition and ack generation is disabled. table 24.6 describes the typical actions when hardware slave address recognition and ack generation is enabled. in the tables, status vector refers to the four upper bits of smb0cn: master, tx mode, sta, and sto. the shown response options are only the typ- ical responses; application-specific procedures are allo wed as long as they conform to the smbus specifi- cation. highlighted responses are allowed by hardwar e but do not conform to the smbus specification. p r sla s data byte data byte a n a s = start p = stop n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) rev. 1.1 205 c8051t620/621/320/321/322/323 table 24.5. smbus status decoding with hardware ack generation disabled (ehack = 0) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was gener- ated. load slave address + r/w into smb0dat. 00x1100 1100 000 a master data or address byte was transmitted; nack received. set sta to restart transfer. 1 0 x 1110 abort transfer. 01x ? 001 a master data or address byte was transmitted; ack received. load next data byte into smb0dat. 00x1100 end transfer with stop. 0 1 x ? end transfer with stop and start another transfer. 11x ? send repeated start. 1 0 x 1110 switch to master receiver mode (clear si without writing new data to smb0dat). 0 0 x 1000 master receiver 1000 1 0 x a master data byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 1000 send nack to indi cate last byte, and send stop. 010 ? send nack to indi cate last byte, and send stop followed by start. 1101110 send ack followed by repeated start. 1011110 send nack to indi cate last byte, and send repeated start. 1001110 send ack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 1 1100 send nack and switch to mas- ter transmitter mode (write to smb0dat before clearing si). 0 0 0 1100 c8051t620/621/320/321/322/323 206 rev. 1.1 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0001 001 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0100 01x a slave byte was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0001 0101 0 x x an illegal stop or bus error was detected while a slave transmission was in progress. clear sto. 00x ? slave receiver 0010 10x a slave address + r/w was received; ack requested. if write, ackno wledge received address 0 0 1 0000 if read, load smb0dat with data byte; ack received address 0 0 1 0100 nack received address. 0 0 0 ? 11x lost arbitration as master; slave address + r/w received; ack requested. if write, ackno wledge received address 0 0 1 0000 if read, load smb0dat with data byte; ack received address 0 0 1 0100 nack received address. 0 0 0 ? reschedule failed transfer; nack received address. 1001110 0001 00x a stop was detected while addressed as a slave trans- mitter or slave receiver. clear sto. 00x ? 11x lost arbitration while attempt- ing a stop. no action required (transfer complete/aborted). 000 ? 0000 1 0 x a slave byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 0000 nack received byte. 0 0 0 ? bus error condition 0010 0 1 x lost arbitration while attempt- ing a repeated start. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0001 0 1 x lost arbitration due to a detected stop. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0000 1 1 x lost arbitration while transmit- ting a data byte as master. abort failed transfer. 0 0 0 ? reschedule failed transfer. 1001110 table 24.5. smbus status decoding with hardware ack generation disabled (ehack = 0) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack rev. 1.1 207 c8051t620/621/320/321/322/323 table 24.6. smbus status decoding with ha rdware ack generation enabled (ehack = 1) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was gener- ated. load slave address + r/w into smb0dat. 00x1100 1100 000 a master data or address byte was transmitted; nack received. set sta to restart transfer. 1 0 x 1110 abort transfer. 01x ? 001 a master data or address byte was transmitted; ack received. load next data byte into smb0dat. 00x1100 end transfer with stop. 0 1 x ? end transfer with stop and start another transfer. 11x ? send repeated start. 1 0 x 1110 switch to master receiver mode (clear si without writing new data to smb0dat). set ack for initial data byte. 0 0 1 1000 master receiver 1000 001 a master data byte was received; ack sent. set ack for next data byte; read smb0dat. 0 0 1 1000 set nack to indicate next data byte as the last data byte; read smb0dat. 0 0 0 1000 initiate repeated start. 1 0 0 1110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100 000 a master data byte was received; nack sent (last byte). read smb0dat; send stop. 0 1 0 ? read smb0dat; send stop followed by start. 1101110 initiate repeated start. 1 0 0 1110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100 c8051t620/621/320/321/322/323 208 rev. 1.1 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0001 001 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0100 01x a slave byte was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0001 0101 0 x x an illegal stop or bus error was detected while a slave transmission was in progress. clear sto. 00x ? slave receiver 0010 00x a slave address + r/w was received; ack sent. if write, set ack for first data byte. 0 0 1 0000 if read, load smb0dat with data byte 0 0 x 0100 01x lost arbitration as master; slave address + r/w received; ack sent. if write, set ack for first data byte. 0 0 1 0000 if read, load smb0dat with data byte 0 0 x 0100 reschedule failed transfer 1 0 x 1110 0001 00x a stop was detected while addressed as a slave trans- mitter or slave receiver. clear sto. 00x ? 01x lost arbitration while attempt- ing a stop. no action required (transfer complete/aborted). 000 ? 0000 0 0 x a slave byte was received. set ack for next data byte; read smb0dat. 0 0 1 0000 set nack for next data byte; read smb0dat. 0 0 0 0000 bus error condition 0010 0 1 x lost arbitration while attempt- ing a repeated start. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0001 0 1 x lost arbitration due to a detected stop. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0000 0 1 x lost arbitration while transmit- ting a data byte as master. abort failed transfer. 0 0 x ? reschedule failed transfer. 10x1110 table 24.6. smbus status decoding with ha rdware ack generation enabled (ehack = 1) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack rev. 1.1 209 c8051t620/621/320/321/322/323 25. uart0 uart0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 uart. enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section ?25.1. enhanced baud rate generation? on page 210). received data buffering allows uart0 to start reception of a second incoming data byte be fore software has finished reading the previous data byte. uart0 has two associated sfrs: serial control regist er 0 (scon0) and serial data buffer 0 (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. writes to sbuf0 always access the transmit register. reads of sbuf0 always access the buffered receive register; it is not possible to read data from the transmit register. with uart0 interrupts enabled, an interrupt is generated each time a transmit is completed (ti0 is set in scon0), or a data byte has been received (ri0 is set in scon0). the uart0 interrupt flags are not cleared by hardware when the cpu vectors to the interr upt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart0 interrupt (transmit complete or receive complete). figure 25.1. uart0 block diagram uart baud rate generator ri scon ri ti rb8 tb8 ren mce smode tx control tx clock send sbuf (tx shift) start data write to sbuf crossbar tx shift zero detector tx irq set qd clr stop bit tb8 sfr bus serial port interrupt ti port i/o rx control start rx clock load sbuf shift 0x1ff rb8 rx irq input shift register (9 bits) load sbuf read sbuf sfr bus crossbar rx sbuf (rx latch) c8051t620/621/320/321/322/323 210 rev. 1.1 25.1. enhanced ba ud rate generation the uart0 baud rate is generated by timer 1 in 8-bit auto-reload mode. the tx clock is generated by tl1; the rx clock is generated by a copy of tl1 (shown as rx timer in figure 25.2), which is not user- accessible. both tx and rx timer overflows are divid ed by two to generate the tx and rx baud rates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is detected on the rx pin. this allows a receive to begin any time a start is detected, independent of the tx timer state. figure 25.2. uart0 baud rate logic timer 1 should be configured for mode 2, 8-bit aut o-reload (see section ?28.1.3. mode 2: 8-bit coun- ter/timer with auto-reload? on p age 243). the timer 1 reload value should be set so that overflows will occur at two times the desired uart baud rate frequenc y. note that timer 1 may be clocked by one of six sources: sysclk, sysclk/4, sysclk/12, sysclk/48, th e external oscillator cloc k/8, or an external input t1. for any given timer 1 clock source, the uart 0 baud rate is determined by equation 25.1-a and equation 25.1-b. equation 25.1. uart0 baud rate where t1 clk is the frequency of the clock supplied to timer 1, and t1h is the high byte of timer 1 (reload value). timer 1 clock frequency is selected as describe d in section ?28. timers? on page 240. a quick ref- erence for typical baud rates and system clock frequenci es is given in table 25.1 through table 25.2. the internal oscillator may st ill generate the system cloc k when the external oscilla tor is driving timer 1. rx timer start detected overflow overflow th1 tl1 tx clock 2 rx clock 2 timer 1 uart uartbaudrate 1 2 -- - t1_overflow_rate ? = t1_overflow_rate t1 clk 256 th1 ? ------------------------- - = a) b) rev. 1.1 211 c8051t620/621/320/321/322/323 25.2. operational modes uart0 provides standard asynchronous, full duplex communication. the uart mode (8-bit or 9-bit) is selected by the s0mode bit (scon0.7). typical uart connection options are shown in figure 25.3. figure 25.3. uart interconnect diagram 25.2.1. 8-bit uart 8-bit uart mode uses a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit. data are transmitted lsb first from the tx0 pin a nd received at the rx0 pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb80 (scon0.2). data transmission begins wh en software writes a data byte to th e sbuf0 register. the ti0 transmit inter- rupt flag (scon0.1) is set at the end of the transmi ssion (the beginning of the st op-bit time). data recep- tion can begin any time after the ren0 receive enable bi t (scon0.4) is set to logic 1. after the stop bit is received, the data byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: ri0 must be logic 0, and if mce0 is logic 1, the stop bit must be logic 1. in the event of a receive data over- run, the first received 8 bits are la tched into the sbuf0 receive register and the following overrun data bits are lost. if these conditions are met, the eight bits of data is stor ed in sbuf0, the stop bit is stored in rb80 and the ri0 flag is set. if these conditio ns are not met, sbuf0 and rb80 will no t be loaded and the ri0 flag will not be set. an interrupt will occur if enabled when ei ther ti0 or ri0 is set. figure 25.4. 8-bit uart timing diagram or rs-232 c8051xxxx rs-232 level xltr tx rx c8051xxxx rx tx mcu rx tx d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space c8051t620/621/320/321/322/323 212 rev. 1.1 25.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programma- ble ninth data bit, and a stop bit. the state of the nint h transmit data bit is determ ined by the value in tb80 (scon0.3), which is assigned by user software. it can be assigned the value of the parity flag (bit p in reg- ister psw) for error detection, or used in multiprocessor communications. on receive, the ninth data bit goes into rb80 (scon0.2) and the stop bit is ignored. data transmission begins when an instruction writes a data byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the tran smission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive enab le bit (scon0.4) is set to 1. after the stop bit is received, the data byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: (1) ri0 must be logic 0, and (2) if mce0 is logic 1, the 9th bit must be logic 1 (when mce0 is logic 0, the state of the ninth data bit is unimportant). if these cond itions are met, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb80, and the ri0 flag is set to 1. if the above conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set to 1. a uart 0 interrupt will occur if enabled when either ti0 or ri0 is set to 1. figure 25.5. 9-bit uart timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8 rev. 1.1 213 c8051t620/621/320/321/322/323 25.3. multiprocessor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave processors by special use of t he ninth data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select th e target(s). an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. setting the mce0 bit (scon0.5) of a slave processor co nfigures its uart such that when a stop bit is received, the uart will generat e an interrupt only if the ninth bit is logic 1 (rb80 = 1) signifying an address byte has been received. in the uart interrupt handler, software will compare the received address with the slave's own assigned 8-bit addre ss. if the addresses match, the slav e will clear its mce0 bit to enable interrupts on the reception of the following data byte (s). slaves that weren't addressed leave their mce0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is rece ived, the addressed slave resets its mce0 bit to ignore all transmis- sions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s). figure 25.6. uart multi-pr ocessor mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx v+ c8051t620/621/320/321/322/323 214 rev. 1.1 sfr address = 0x98; bit-addressable sfr definition 25.1. scon0: serial port 0 control bit76543210 name s0mode mce0 ren0 tb80 rb80 ti0 ri0 type r/w r r/w r/w r/w r/w r/w r/w reset 01000000 bit name function 7s0mode serial port 0 operation mode. selects the uart0 operation mode. 0: 8-bit uart with variable baud rate. 1: 9-bit uart with variable baud rate. 6 unused unused . read = 1b, write = don?t care. 5mce0 multiprocessor comm unication enable. the function of this bit is dependent on the serial port 0 operation mode: mode 0: checks for valid stop bit. 0: logic level of stop bit is ignored. 1: ri0 will only be activated if stop bit is logic level 1. mode 1: multiprocessor communications enable. 0: logic level of ninth bit is ignored. 1: ri0 is set and an interrupt is genera ted only when the ninth bit is logic 1. 4ren0 receive enable. 0: uart0 reception disabled. 1: uart0 reception enabled. 3tb80 ninth transmission bit. the logic level of this bit will be sent as the ninth transmission bi t in 9-bit uart mode (mode 1). unused in 8-bit mode (mode 0). 2rb80 ninth receive bit. rb80 is assigned the value of the stop bit in mode 0; it is assigned the value of the 9th data bit in mode 1. 1ti0 transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in 8-bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software. 0ri0 receive interrupt flag. set to 1 by hardware when a byte of data has been received by uart0 (set at the stop bit sampling time). when the uart0 in terrupt is enabled, setting this bit to 1 causes the cpu to vector to the uart0 in terrupt service routine. this bit must be cleared manually by software. rev. 1.1 215 c8051t620/621/320/321/322/323 sfr address = 0x99 sfr definition 25.2. sbuf0: seri al (uart0) port data buffer bit76543210 name sbuf0[7:0] type r/w reset 00000000 bit name function 7:0 sbuf0[7:0] serial data buffer bits 7?0 (msb?lsb). this sfr accesses two registers; a transmit shift register and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is held for serial transmission. writing a byte to sbuf0 initiates the transmission. a read of sbuf0 returns the contents of the receive latch. c8051t620/621/320/321/322/323 216 rev. 1.1 table 25.1. timer settings for standard baud rates using the internal 24.5 mhz oscillator frequency: 24.5 mhz target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) sysclk from internal osc. 230400 ?0.32% 106 sysclk xx 2 1 0xcb 115200 ?0.32% 212 sysclk xx 1 0x96 57600 0.15% 426 sysclk xx 1 0x2b 28800 ?0.32% 848 sysclk/4 01 0 0x96 14400 0.15% 1704 sysclk/12 00 0 0xb9 9600 ?0.32% 2544 sysclk/12 00 0 0x96 2400 ?0.32% 10176 sysclk/48 10 0 0x96 1200 0.15% 20448 sysclk/48 10 0 0x2b notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 28.1 . 2. x = don?t care. table 25.2. timer settings for standard baud rates using an external 22.1184 mhz oscillator frequency: 22.1184 mhz target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) sysclk from external osc. 230400 0.00% 96 sysclk xx 2 10xd0 115200 0.00% 192 sysclk xx 1 0xa0 57600 0.00% 384 sysclk xx 1 0x40 28800 0.00% 768 sysclk / 12 00 0 0xe0 14400 0.00% 1536 sysclk / 12 00 0 0xc0 9600 0.00% 2304 sysclk / 12 00 0 0xa0 2400 0.00% 9216 sysclk / 48 10 0 0xa0 1200 0.00% 18432 sysc lk / 48 10 0 0x40 sysclk from internal osc. 230400 0.00% 96 extclk / 8 11 0 0xfa 115200 0.00% 192 extclk / 8 11 0 0xf4 57600 0.00% 384 extclk / 8 11 0 0xe8 28800 0.00% 768 extclk / 8 11 0 0xd0 14400 0.00% 1536 extclk / 8 11 0 0xa0 9600 0.00% 2304 extclk / 8 11 0 0x70 notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 28.1 . 2. x = don?t care. rev. 1.1 217 c8051t620/621/320/321/322/323 26. uart1 uart1 is an asynchronous, full duplex serial port offeri ng a variety of data formatting options. a dedicated baud rate generator with a 16-bit timer and selectable prescaler is included, which can generate a wide range of baud rates (details in section ?26.1. baud rate generator? on page 217). a received data fifo allows uart1 to receive up to three data bytes before data is lost and an overflow occurs. uart1 has six associated sfrs. three are used for the baud rate generator (sbcon1, sbrlh1, and sbrll1), two are used for data formatting, control, and status functions (scon1, smod1), and one is used to send and receive data (sbuf1). the single sbuf1 location provides access to both the transmit holding register and the receive fifo. writes to sbuf1 always access the transmit holding register. reads of sbuf1 always access the first byte of the receive fifo; it is not possible to read data from the transmit holding register. with uart1 interrupts enabled, an interrupt is generated each time a transmit is completed (ti1 is set in scon1), or a data byte has been received (ri1 is set in scon1). the uart1 interrupt flags are not cleared by hardware when the cpu vectors to the interr upt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart1 interrupt (transmit complete or receive complete). note that if additional bytes are available in the receive fifo, the ri1 bit cannot be cleared by software. figure 26.1. uart1 block diagram 26.1. baud rate generator the uart1 baud rate is generated by a dedicated 16-bi t timer which runs from the controller?s core clock (sysclk), and has prescaler options of 1, 4, 12, or 48. the timer and prescaler options combined allow for a wide selection of baud rates over many sysclk frequencies. the baud rate generator is configured using th ree registers: sbcon1, sbrlh1, and sbrll1. the uart1 baud rate generator control register (sbcon1, sfr definition ) enables or disables the baud rate generator, and selects the prescaler value for the timer. the baud rate generator must be enabled for uart1 to function. registers sbrlh1 and sbrll1 contain a 16-bit reload value for the dedicated 16-bit timer. the internal timer counts up from the reload value on every clock tick. on timer overflows (0xffff to 0x0000), the timer is reloaded. for reliable uart o peration, it is recommended that the uart baud rate is not configured for baud rates faster than sysclk/16. the baud rate for uart1 is defined in equation 26.1. sbuf1 tx holding register rx fifo (3 deep) tx logic rx logic write to sbuf1 read of sbuf1 tx1 rx1 smod1 mce1 s1pt1 s1pt0 pe1 s1dl1 s1dl0 xbe1 sbl1 data formatting scon1 ovr1 perr1 thre1 ren1 tbx1 rbx1 ti1 ri1 control / status uart1 interrupt timer (16-bit) pre-scaler (1, 4, 12, 48) sysclk sbrlh1 sbrll1 overflow sbcon1 sb1run sb1ps1 sb1ps0 en baud rate generator c8051t620/621/320/321/322/323 218 rev. 1.1 equation 26.1. uart1 baud rate a quick reference for typical baud rates and sy stem clock frequencies is given in table 26.1. 26.2. data format uart1 has a number of available options for data form atting. data transfers begin with a start bit (logic low), followed by the data bits (sent lsb-first), a parity or extra bit (if selected), and end with one or two stop bits (logic high). the data length is variable between 5 and 8 bits. a parity bit can be appended to the data, and automatically generated and detected by hardware for even, odd, mark, or space parity. the stop bit length is selectable between short (1 bit time) and long (1.5 or 2 bit times), and a multi-processor com- munication mode is available for implementing networ ked uart buses. all of the data formatting options can be configured using the smod1 register, shown in sfr definition . figure 26.2 shows the timing for a uart1 transaction without parity or an extra bit enabl ed. figure 26.3 shows the timing for a uart1 trans- action with parity enabled (pe1 = 1). figure 26.4 is an example of a uart1 transaction when the extra bit is enabled (xbe1 = 1). note that the extra bit feature is not available when parity is enabled, and the sec- ond stop bit is only an option for data lengths of 6, 7, or 8 bits. table 26.1. baud rate generator settings for standard baud rates target baud rate (bps) actual baud rate (bps) baud rate error oscillator divide factor sb1ps[1:0] (prescaler bits) reload value in sbrlh1:sbrll1 sysclk = 12 mhz 230400 230769 0.16% 52 11 0xffe6 115200 115385 0.16% 104 11 0xffcc 57600 57692 0.16% 208 11 0xff98 28800 28846 0.16% 416 11 0xff30 14400 14388 0.08% 834 11 0xfe5f 9600 9600 0.0% 1250 11 0xfd8f 2400 2400 0.0% 5000 11 0xf63c 1200 1200 0.0% 10000 11 0xec78 sysclk = 24 mhz 230400 230769 0.16% 104 11 0xffcc 115200 115385 0.16% 208 11 0xff98 57600 57692 0.16% 416 11 0xff30 28800 28777 0.08% 834 11 0xfe5f 14400 14406 0.04% 1666 11 0xfcbf 9600 9600 0.0% 2500 11 0xfb1e 2400 2400 0.0% 10000 11 0xec78 1200 1200 0.0% 20000 11 0xd8f0 sysclk = 48 mhz 230400 230769 0.16% 208 11 0xff98 115200 115385 0.16% 416 11 0xff30 57600 57554 0.08% 834 11 0xfe5f 28800 28812 0.04% 1666 11 0xfcbf 14400 14397 0.02% 3334 11 0xf97d 9600 9600 0.0% 5000 11 0xf63c 2400 2400 0.0% 20000 11 0xd8f0 1200 1200 0.0% 40000 11 0xb1e0 baud rate sysclk 65536 (sbrlh1:sbrll1) ? ?? ----------------------------------------------------------- ---------------- 1 2 -- - ? 1 prescaler ----------- ---------- - ? = rev. 1.1 219 c8051t620/621/320/321/322/323 figure 26.2. uart1 timing without parity or extra bit figure 26.3. uart1 timing with parity figure 26.4. uart1 timing with extra bit 26.3. configurat ion and operation uart1 provides standard asynchronous, full duplex communication. it can operate in a point-to-point serial communications application, or as a node on a mult i-processor serial interface. to operate in a point- to-point application, where there ar e only two devices on the serial bus, the mce1 bit in smod1 should be cleared to 0. for o peration as part of a mult i-processor communications bu s, the mce1 and xbe1 bits should both be set to 1. in both types of applicatio ns, data is transmitted from the microcontroller on the tx1 pin, and received on the rx1 pin. the tx1 and rx1 pins are configured using the crossbar and the port i/o registers, as detailed in sectio n ?22. port input/output? on page 133. in typical uart communications, the transmit (tx) outp ut of one device is connec ted to the receive (rx) input of the other device, either directly or th rough a bus transceiver, as shown in figure 26.5. d 1 d 0 d n-2 d n-1 start bit mark stop bit 1 bit times space n bits; n = 5, 6, 7, or 8 stop bit 2 optional d 1 d 0 d n-2 d n-1 parity start bit mark stop bit 1 bit times space n bits; n = 5, 6, 7, or 8 stop bit 2 optional d 1 d 0 d n-2 d n-1 extra start bit mark stop bit 1 bit times space n bits; n = 5, 6, 7, or 8 stop bit 2 optional c8051t620/621/320/321/322/323 220 rev. 1.1 figure 26.5. typical uart interconnect diagram 26.3.1. data transmission data transmission is double-buffered, and begins when software writes a data byte to the sbuf1 register. writing to sbuf1 places data in the transmit holdin g register, and the transmit holding register empty flag (thre1) will be cleared to 0. if the uarts shift register is empty (i.e. no transmission is in progress) the data will be placed in the shift register, and the th re1 bit will be set to 1. if a transmission is in prog- ress, the data will remain in the transmit holding register until the current transmission is complete. the ti1 transmit interrupt flag (scon1.1) will be set at the end of any transmission (the beginning of the stop- bit time). if enabled, an inte rrupt will occur when ti1 is set. if the extra bit function is enabled (xbe1 = 1) and the parity function is disabled (pe1 = 0), the value of the tbx1 (scon1.3) bit will be sent in the extra bit positi on. when the parity functi on is enabled (pe1 = 1), hardware will generate the parity bit accord ing to the selected parity type (selected with s1pt[1:0]), and append it to the data field. note: when parity is enabled, the extra bit function is not available. 26.3.2. data reception data reception can begin any time after the ren1 receiv e enable bit (scon1.4) is set to logic 1. after the stop bit is received, the data byte will be stored in th e receive fifo if the following conditions are met: the receive fifo (3 bytes deep) must not be full, and the stop bit(s) must be logic 1. in the event that the receive fifo is full, the incoming byte will be lost, and a receive fi fo overrun error will be generated (ovr1 in register scon1 will be set to logic 1). if the stop bit(s) were logic 0, the incoming data will not be stored in the receive fifo. if the reception conditions are met, the data is stored in the receive fifo, and the ri1 flag will be set. note: when mce1 = 1, ri1 will on ly be set if the extra bit was equal to 1. data can be read from the receive fifo by reading the sbuf1 register. the sbuf1 register represents the oldest byte in the fifo. after sbuf1 is read, the next byte in the fifo is immediately loaded into sbuf1, and space is made available in the fifo for another inco ming byte. if enabled, an interrupt will occur when ri1 is set. ri1 can only be cleared to '0' by software wh en there is no more inform ation in the fifo. the rec- ommended procedure to empty the fifo contents is: 1. clear ri1 to '0' 2. read sbuf1 3. check ri1, and repeat at step 1 if ri1 is set to '1'. if the extra bit function is en abled (xbe1 = 1) and the parity function is disabled (pe1 = 0), the extra bit for the oldest byte in the fifo can be read from the rbx1 bit (scon1.2). if the extra bit function is not enabled, the value of the stop bit fo r the oldest fifo byte will be presen ted in rbx1. when the parity func- tion is enabled (pe1 = 1) , hardware will check the received parity bit against the selected parity type (selected with s1pt[1:0]) when receivi ng data. if a byte with parity error is received, the perr1 flag will be set to 1. this flag must be cleared by software. note: when parity is enabled, the extra bit function is not available. or rs-232 c8051fxxx rs-232 level translator tx rx c8051fxxx rx tx mcu rx tx pc com port rev. 1.1 221 c8051t620/621/320/321/322/323 26.3.3. mult iprocessor communications uart1 supports multiprocessor communication between a master processor and one or more slave pro- cessors by special use of the extra data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target (s). an address byte differs from a data byte in that its extra bit is logic 1; in a data byte, the extra bit is always set to logic 0. setting the mce1 bit (smod1.7) of a slave processor c onfigures its uart such that when a stop bit is received, the uart will generate an interrupt only if the extra bit is logic 1 (rbx1 = 1) signifying an address byte has been rece ived. in the uart interr upt handler, software w ill compare the received address with the slave's own assigned address. if the addres ses match, the slave will clear its mce1 bit to enable interrupts on the reception of the following da ta byte(s). slaves that we ren't addressed leave their mce1 bits set and do not generate interrupts on the rece ption of the following data bytes, thereby ignoring the data. once the entire message is received, the addressed slave resets its mce1 bit to ignore all trans- missions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex transmission between the original master and slave(s). figure 26.6. uart multi-pr ocessor mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx v+ c8051t620/621/320/321/322/323 222 rev. 1.1 sfr address = 0xd2 sfr definition 26.1. sc on1: uart1 control bit76543210 name ovr1 perr1 thre1 ren1 tbx1 rbx1 ti1 ri1 type r/w r/w r r/w r/w r/w r/w r/w reset 00100000 bit name function 7ovr1 receive fifo overrun flag. this bit indicates a receive fifo overrun condition, where an incoming character is discarded due to a full fifo. this bit must be cleared to 0 by software. 0: receive fifo overrun has not occurred. 1: receive fifo overrun has occurred. 6 perr1 parity error flag. when parity is enabled, this bit indicates that a parity error has occurred. it is set to 1 when the parity of the oldest byte in the fifo does not match the selected parity type. this bit must be cleared to 0 by software. 0: parity error has not occurred. 1: parity error has occurred. 5 thre1 transmit holding register empty flag. 0: transmit holding register not empty - do not write to sbuf1. 1: transmit holding register empty - it is safe to write to sbuf1. 4ren1 receive enable. this bit enables/disables the uart receiver. when disabled, bytes can still be read from the receive fifo. 0: uart1 reception disabled. 1: uart1 reception enabled. 3 tbx1 extra transmission bit. the logic level of this bit will be assigned to the extra transmission bit when xbe1 = 1. this bit is not used when parity is enabled. 2 rbx1 extra receive bit. rbx1 is assigned the va lue of the extra bit when xbe1 = 1. if xbe1 is cleared to 0, rbx1 is assigned the logic level of the first stop bit. this bit is not valid when parity is enabled. 1ti1 transmit interrupt flag. set to a 1 by hardware after data has been transmitted at the beginning of the stop bit. when the uart1 interrupt is enabled, setting this bit c auses the cpu to vector to the uart1 interrupt service routine. this bit must be cleared manually by software. 0ri1 receive interrupt flag. set to 1 by hardware when a byte of data has been received by uart1 (set at the stop bit sam- pling time). when the uart1 interrupt is enabled, setting this bit to 1 causes the cpu to vector to the uart1 interrupt service routine. this bit must be cleared manually by software. note that ri1 will remain set to '1' as long as there is still data in the uart fifo. after the last byte has been shifted from the fifo to sbuf1, ri1 can be cleared. rev. 1.1 223 c8051t620/621/320/321/322/323 sfr address = 0xe5 sfr definition 26.2. smod1: uart1 mode bit76543210 name mce1 s1pt[1:0] pe1 s1dl[1:0] xbe1 sbl1 type r/w r/w r/w r/w r/w r/w reset 00001100 bit name function 7mce1 multiprocessor comm unication enable. 0: ri will be activated if stop bit(s) are 1. 1: ri will be activated if stop bit(s) and ex tra bit are 1 (extra bi t must be e nabled using xbe1). note: this function is not available when hardware parity is enabled. 6:5 s1pt[1:0] parity type bits. 00: odd 01: even 10: mark 11: space 4 pe1 parity enable. this bit activates hardware parity generation and checking. the parity type is selected by bits s1pt1-0 when parity is enabled. 0: hardware parity is disabled. 1: hardware parity is enabled. 3:2 s1dl[1:0] data length. 00: 5-bit data 01: 6-bit data 10: 7-bit data 11: 8-bit data 1 xbe1 extra bit enable. when enabled, the valu e of tbx1 will be app ended to the data field. 0: extra bit disabled. 1: extra bit enabled. 0sbl1 stop bit length. 0: short - stop bit is active for one bit time. 1: long - stop bit is active for two bit times (d ata length = 6, 7, or 8 bits), or 1.5 bit times (data length = 5 bits). c8051t620/621/320/321/322/323 224 rev. 1.1 sfr address = 0xd3 sfr definition 26.3. sbuf1: uart1 data buffer bit76543210 name sbuf1[7:0] type r/w reset 00000000 bit name description write read 7:0 sbuf1[7:0 ] serial data buffer bits. this sfr is used to both send data from the uart and to read received data from the uart1 receive fifo. writing a byte to sbuf1 initiates the transmission. when data is written to sbuf1, it first goes to the transmit holding register, where it is held for serial transmission. when the transmit shift register is available, data is trans- ferred into the shift regis- ter, and sbuf1 may be written again. reading sbuf1 retrieves data from the receive fifo. when read, the old- est byte in the receive fifo is returned, and removed from the fifo. up to three bytes may be held in the fifo. if there are additional bytes avail- able in the fifo, the ri1 bit will remain at logic 1, even after being cleared by software. rev. 1.1 225 c8051t620/621/320/321/322/323 sfr address = 0xac sfr address = 0xb5 sfr definition 26.4. sbcon1: uart1 baud rate generator control bit76543210 name reserved sb1run reserved reserved reserved reserved sb1ps[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 reserved reserved. read = 0b. must write 0b. 6 sb1run baud rate generator enable. 0: baud rate generator is di sabled. uart1 will not function. 1: baud rate generator is enabled. 5:2 reserved reserved. read = 0000b. must write 0000b. 1:0 sb1ps[1:0] baud rate prescaler select. 00: prescaler = 12 01: prescaler = 4 10: prescaler = 48 11: prescaler = 1 sfr definition 26.5. sbrlh1: uart 1 baud rate generator high byte bit76543210 name sbrlh1[7:0] type r/w reset 00000000 bit name function 7:0 sbrlh1[7:0] uart1 baud rate reload high bits. high byte of reload value for uart1 baud rate generator. c8051t620/621/320/321/322/323 226 rev. 1.1 sfr address = 0xb4 sfr definition 26.6. sb rll1: uart1 baud rate generator low byte bit76543210 name sbrll1[7:0] type r/w reset 00000000 bit name function 7:0 sbrll1[7:0] uart1 baud rate reload low bits. low byte of reload value fo r uart1 baud rate generator. rev. 1.1 227 c8051t620/621/320/321/322/323 27. enhanced serial pe ripheral interface (spi0) the enhanced serial peripheral interface (spi0) prov ides access to a flexible, full-duplex synchronous serial bus. spi0 can operate as a master or slave devi ce in both 3-wire or 4-wire modes, and supports mul- tiple masters and slaves on a single spi bus. the slav e-select (nss) signal can be configured as an input to select spi0 in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the spi bus when more than one master attempts simultaneous data transfers. nss can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. additional gen- eral purpose port i/o pins can be used to se lect multiple slave dev ices in master mode. figure 27.1. spi block diagram sfr bus data path control sfr bus write spi0dat receive data buffer spi0dat 0 1 2 3 4 5 6 7 shift register spi control logic spi0ckr scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 spi0cfg spi0cn pin interface control pin control logic c r o s s b a r port i/o read spi0dat spi irq tx data rx data sck mosi miso nss transmit data buffer clock divide logic sysclk ckpha ckpol slvsel nssmd1 nssmd0 spibsy msten nssin srmt rxbmt spif wcol modf rxovrn txbmt spien c8051t620/621/320/321/322/323 228 rev. 1.1 27.1. signal descriptions the four signals used by spi0 (mosi, miso, sck, nss) are described below. 27.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output fr om a master device and an input to slave devices. it is used to serially transfer data from the master to th e slave. this signal is an output when spi0 is operat- ing as a master and an input when spi0 is operating as a slave. data is transferred most-significant bit first. when configured as a master, mosi is driven by the msb of the shift register in both 3- and 4-wire mode. 27.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output fr om a slave device and an input to the master device. it is used to serially transfer data from the slave to the master. this signal is an input when spi0 is operat- ing as a master and an output when spi0 is operating as a slave. data is transferred most-significant bit first. the miso pin is placed in a high-impedance stat e when the spi module is disabled and when the spi operates in 4-wire mode as a slave that is not selected. when acting as a slave in 3-wire mode, miso is always driven by the msb of the shift register. 27.1.3. serial clock (sck) the serial clock (sck) signal is an output from the mast er device and an input to slave devices. it is used to synchronize the transfer of data between the mast er and slave on the mosi and miso lines. spi0 gen- erates this signal when operating as a master. the sck signal is ignored by a spi slave when the slave is not selected (nss = 1) in 4-wire slave mode. 27.1.4. slave select (nss) the function of the slave-select (nss) signal is dependent on the setting of the nssmd1 and nssmd0 bits in the spi0cn register. there are three possible modes that can be selected with these bits: 1. nssmd[1:0] = 00: 3-wire master or 3-wire slave mode: spi0 operates in 3-wire mode, and nss is disabled. when operating as a slave device, spi0 is always selected in 3-wire mode. since no select signal is present, spi0 must be the only slave on th e bus in 3-wire mode. this is intended for point-to- point communication between a master and one slave. 2. nssmd[1:0] = 01: 4-wire slave or multi-master mode: spi0 operates in 4-wire mode, and nss is enabled as an input. when operating as a slave, nss selects the spi0 device. when operating as a master, a 1-to-0 transition of the nss signal disabl es the master function of spi0 so that multiple master devices can be used on the same spi bus. 3. nssmd[1:0] = 1x: 4-wire master mode: spi0 oper ates in 4-wire mode, and nss is enabled as an output. the setting of nssmd0 determ ines what logic level the nss pin will output. this configuration should only be used when operating spi0 as a master device. see figure 27.2, figure 27.3, and figure 27.4 for typi cal connection diagrams of the various operational modes. note that the setting of nssmd bits affects the pinout of the device. when in 3-wire master or 3-wire slave mode, the nss pin will not be mapped by the crossbar. in a ll other modes, the nss signal will be mapped to a pin on the device. see section ?22. port input/output? on page 133 for general purpose port i/o and crossbar information. 27.2. spi0 master mode operation a spi master device initiates all data transfers on a spi bus. spi0 is placed in master mode by setting the master enable flag (msten, spi0cn.6). writing a byte of data to the spi0 data register (spi0dat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. the spi0 master immediately shifts out the data serially on the mosi line while providing the serial clock on sck. rev. 1.1 229 c8051t620/621/320/321/322/323 the spif (spi0cn.7) flag is set to logic 1 at the end of the transfer. if interrupts are enabled, an interrupt request is generated when the spif flag is set. while the spi0 master transfers data to a slave on the mosi line, the addressed spi slave device simultaneously transfers the contents of its shift register to the spi master on the miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit- complete and receive-data-ready flag. the data byte received from the slave is transferred msb-first into the master's shift register. when a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading spi0dat. when configured as a master, spi0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. the default, multi-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in this mode, nss is an input to the device, and is used to disable the master spi0 when another mast er is accessing the bus. when nss is pulled low in this mode, msten (spi0cn.6) and spien (spi0cn.0) ar e set to 0 to disable the spi master device, and a mode fault is gene rated (modf, spi0cn.5 = 1). mode fault will generate an interrupt if enabled. spi0 must be manually re-enabled in software under these ci rcumstances. in multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. in multi-mas- ter mode, slave devices can be addressed individually (if needed) using general-purpose i/o pins. figure 27.2 shows a connection diagram between two master devices in multiple-mas ter mode. 3-wire single-master mode is active when nssmd1 (s pi0cn.3) = 0 and nssmd0 ( spi0cn.2) = 0. in this mode, nss is not used, and is not mapped to an exte rnal port pin through the crossbar. any slave devices that must be addressed in this mode should be selected using general-purpose i/o pins. figure 27.3 shows a connection diagram between a master device in 3-wire master mode and a slave device. 4-wire single-master mode is active when nssmd1 (spi0c n.3) = 1. in this mode, nss is configured as an output pin, and can be used as a slave-select signal for a single spi dev ice. in this mode, the output value of nss is controlled (in software) with the bit n ssmd0 (spi0cn.2). additional slave devices can be addressed using general-purpose i/o pins. figure 27.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. figure 27.2. multiple-master mode connection diagram figure 27.3. 3-wire single master and 3-wire single slave mode connection diagram master device 2 master device 1 mosi miso sck miso mosi sck nss gpio nss gpio slave device master device mosi miso sck miso mosi sck c8051t620/621/320/321/322/323 230 rev. 1.1 figure 27.4. 4-wire single master mode and 4-wire slave mode connection diagram 27.3. spi0 slave mode operation when spi0 is enabled and not configured as a master, it will operate as a spi slave. as a slave, bytes are shifted in through the mosi pin and out through the mi so pin by a master device controlling the sck sig- nal. a bit counter in the spi0 logic counts sck edges. when 8 bits have been shifted through the shift reg- ister, the spif flag is set to logic 1, and the byte is copied into the receive buffer. data is read from the receive buffer by reading spi0dat. a slave device cannot initiate transfers. data to be transferred to the master device is pre-loaded into the shift register by writing to spi0dat. writes to spi0dat are double- buffered, and are placed in the transmit buffer first. if the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. when the sh ift register already contains data, the spi will load the shift register wi th the transmit buffer?s contents af ter the last sck edg e of the next (or current) spi transfer. when configured as a slave, spi0 can be configured for 4-wire or 3-wire operation. the default, 4-wire slave mode, is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in 4-wire mode, the nss signal is routed to a port pin and configured as a digital input. spi0 is enabled when nss is logic 0, and disabled when nss is logic 1. th e bit counter is reset on a falling ed ge of nss. note that the nss sig- nal must be driven low at least 2 system clocks before the first active edge of sck for each byte transfer. figure 27.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master device. 3-wire slave mode is active when nssmd1 (spi0c n.3) = 0 and nssmd0 (spi0cn.2) = 0. nss is not used in this mode, and is not mapped to an external port pin through the crossbar. since there is no way of uniquely addressing the device in 3-wire slave mode , spi0 must be the only slav e device present on the bus. it is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. th e bit counter can only be reset by disabling and re- enabling spi0 with the spien bit. figure 27.3 shows a connection diagram between a slave device in 3- wire slave mode and a master device. slave device master device mosi miso sck miso mosi sck nss nss gpio slave device mosi miso sck nss rev. 1.1 231 c8051t620/621/320/321/322/323 27.4. spi0 interrupt sources when spi0 interrupts are e nabled, the following four flags will gener ate an interrupt when they are set to logic 1: all of the following bits must be cleared by software. ? the spi interrupt flag, spif (spi0cn.7) is set to logic 1 at the end of each byte transfer. this flag can occur in all spi0 modes. ? the write collision flag, wcol (spi0cn.6) is set to logic 1 if a write to spi 0dat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occurs, the write to spi0dat will be ignored, and the transmit buffer will not be writte n.this flag can occur in all spi0 modes. ? the mode fault flag modf (spi0cn.5) is set to logi c 1 when spi0 is configured as a master, and for multi-master mode and the nss pin is pulled low. when a mode fault occurs, the msten and spien bits in spi0cn are set to logic 0 to disable spi0 and allow another master device to access the bus. ? the receive overrun flag rxovrn (spi0cn.4) is se t to logic 1 when configured as a slave, and a transfer is completed and the rece ive buffer still holds an unread byte from a prev ious transfer. the new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. the data byte which caused the overrun is lost. 27.5. serial clock phase and polarity four combinations of serial clock phase and polarity can be selected using the clock control bits in the spi0 configuration register (spi0cfg). the ckpha bit ( spi0cfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spi0cfg.4) selects between an active-high or active-low clock. both master and slave devices must be config ured to use the same clock phase and polarity. spi0 should be disabled (by clearing the spien bit, spi0 cn.0) when changing the clock phase or polarity. the clock and data line relationships for master mode are shown in figure 27.5. for slave mode, the clock and data relationships are shown in figure 27.6 and figure 27.7. note that ckpha should be set to 0 on both the master and slave spi w hen communicating be tween two silicon labs c8051 devices. the spi0 clock rate register (spi0c kr) as shown in sfr definition 27.3 controls the master mode serial clock frequency. this register is ignored when operating in slave mode. when the spi is configured as a master, the maximum data transfer rate (bits/sec) is one-half the s ystem clock frequency or 12.5 mhz, whichever is slower. when the spi is configured as a sl ave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency , provided that the master issues sck, nss (in 4- wire slave mode), and the serial input data synchrono usly with the slave?s system clock. if the master issues sck, nss, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. in the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the spi slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master i ssues sck, nss, and the serial input data synchronously with the slave?s system clock. c8051t620/621/320/321/322/323 232 rev. 1.1 figure 27.5. master mode data/clock timing figure 27.6. slave mode data/clock timing (ckpha = 0) sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi nss (must remain high in multi-master mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi sck (ckpol=0, ckpha=0) sck (ckpol=1, ckpha=0) rev. 1.1 233 c8051t620/621/320/321/322/323 figure 27.7. slave mode data/clock timing (ckpha = 1) 27.6. spi special function registers spi0 is accessed and controlled through four special function registers in the system controller: spi0cn control register, spi0dat data register, spi0cfg configuration register, and spi0ckr clock rate register. the four special function registers related to the operation of the spi0 bus are described in the following figures. sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi c8051t620/621/320/321/322/323 234 rev. 1.1 sfr address = 0xa1 sfr definition 27.1. spi0c fg: spi0 configuration bit7654321 0 name spibsy msten ckpha ckpol slvsel nssin srmt rxbmt type r r/w r/w r/w r r r r reset 0000011 1 bit name function 7 spibsy spi busy. this bit is set to logic 1 when a spi transf er is in progress (master or slave mode). 6 msten master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. 5 ckpha spi0 clock phase. 0: data centered on first edge of sck period. * 1: data centered on second edge of sck period. * 4ckpol spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. 3 slvsel slave selected flag. this bit is set to logic 1 whenever the nss pin is low indicating spi0 is the selected slave. it is cleared to logic 0 when nss is high (slave not selected). this bit does not indicate the instantaneous value at the nss pin, but rather a de-glitched ver- sion of the pin input. 2 nssin nss instantaneous pin input. this bit mimics the instantaneous value that is present on the nss port pin at the time that the register is read. this input is not de-glitched. 1srmt shift register empty (valid in slave mode only). this bit will be set to logic 1 when all data has been transferred in/out of the shift register, and there is no new information avai lable to read from the transmit buffer or write to the receive buffer . it returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on sck. srmt = 1 when in master mode. 0 rxbmt receive buffer empty (valid in slave mode only). this bit will be set to logic 1 when the re ceive buffer has been read and contains no new information. if there is new informatio n available in the receive buffer that has not been read, this bit will return to logic 0. rxbm t = 1 when in master mode. note: in slave mode, data on mosi is sampled in the center of each data bit. in master mode, data on miso is sampled one sysclk before the end of each data bit, to provide maximum settling time for the slave device. see table 27.1 for timing parameters. rev. 1.1 235 c8051t620/621/320/321/322/323 sfr address = 0xf8; bit-addressable sfr definition 27.2. spi0cn: spi0 control bit7654321 0 name spif wcol modf rxovrn nssmd[1:0] txbmt spien type r/w r/w r/w r/w r/w r r/w reset 0000011 0 bit name function 7 spif spi0 interrupt flag. this bit is set to logic 1 by hardware at the end of a data transfer. if spi interrupts are enabled, an interrupt will be ge nerated. this bit is not automatically cleared by hardware, and must be cleared by software. 6wcol write collision flag. this bit is set to logic 1 if a write to spi0dat is attempted when txbmt is 0. when this occurs, the write to spi0dat will be i gnored, and the transmit buffer will not be written. if spi interrupts are enabled, an in terrupt will be generated. this bit is not automatically cleared by hardware, and must be cleared by software. 5modf mode fault flag. this bit is set to logic 1 by hardware when a master mode co llision is detected (nss is low, msten = 1, and nssmd[1:0] = 01). if spi interrupts are enabled, an interrupt will be gener ated. this bit is not automati cally cleared by hardware, and must be cleared by software. 4 rxovrn receive overrun flag (valid in slave mode only). this bit is set to logic 1 by hardware when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the spi0 shift register. if spi interrupts are enabled, an interrupt will be generated. this bit is not automatically cleared by hardware, and must be cleared by software. 3:2 nssmd[1:0] slave select mode. selects between the following nss operation modes: (see section 27.2 and section 27.3). 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (d efault). nss is an input to the device. 1x: 4-wire single-master mode. nss sign al is mapped as an output from the device and will assume the value of nssmd0. 1 txbmt transmit buffer empty. this bit will be set to logic 0 when new da ta has been written to the transmit buffer. when data in the transmit buffer is transferred to the spi shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. 0 spien spi0 enable. 0: spi disabled. 1: spi enabled. c8051t620/621/320/321/322/323 236 rev. 1.1 sfr address = 0xa2 sfr address = 0xa3 sfr definition 27.3. spi 0ckr: spi0 clock rate bit7654321 0 name scr[7:0] type r/w reset 0000000 0 bit name function 7:0 scr[7:0] spi0 clock rate. these bits determine the frequency of the sck output when the spi0 module is configured for master mode operation. the sck clock frequency is a divided ver- sion of the system clock, and is given in the following equation, where sysclk is the system clock frequency and spi0ckr is the 8-bit value held in the spi0ckr register. for 0 <= spi0ckr <= 255 example: if sysclk = 2 mhz and spi0ckr = 0x04, sfr definition 27.4. spi0dat: spi0 data bit7654321 0 name spi0dat[7:0] type r/w reset 0000000 0 bit name function 7:0 spi0dat[7:0] spi0 transmit and receive data. the spi0dat register is used to transmit and receive spi0 data. writing data to spi0dat places the data into the transmi t buffer and initiates a transfer when in master mode. a read of spi0dat returns the contents of the receive buffer. f sck sysclk 2 spi0ckr[7:0] 1 + ?? ? ------------------- --------------------------------------- - = f sck 2000000 241 + ?? ? -------------------------- = f sck 200 khz = rev. 1.1 237 c8051t620/621/320/321/322/323 figure 27.8. spi master timing (ckpha = 0) figure 27.9. spi master timing (ckpha = 1) sck* t mckh t mckl mosi t mis miso * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mih sck* t mckh t mckl miso t mih mosi * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mis c8051t620/621/320/321/322/323 238 rev. 1.1 figure 27.10. spi slave timing (ckpha = 0) figure 27.11. spi slave timing (ckpha = 1) sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t slh t sez t sdz rev. 1.1 239 c8051t620/621/320/321/322/323 table 27.1. spi slave timing parameters parameter description min max units master mode timing (see figure 27.8 and figure 27.9) t mckh sck high time 1 x t sysclk ?ns t mckl sck low time 1 x t sysclk ?ns t mis miso valid to sck shift edge 1 x t sysclk + 20 ? ns t mih sck shift edge to miso change 0 ? ns slave mode timing (see figure 27.10 and figure 27.11) t se nss falling to first sck edge 2 x t sysclk ?ns t sd last sck edge to nss rising 2 x t sysclk ?ns t sez nss falling to miso valid ? 4 x t sysclk ns t sdz nss rising to miso high-z ? 4 x t sysclk ns t ckh sck high time 5 x t sysclk ?ns t ckl sck low time 5 x t sysclk ?ns t sis mosi valid to sck sample edge 2 x t sysclk ?ns t sih sck sample edge to mosi change 2 x t sysclk ?ns t soh sck shift edge to miso change ? 4 x t sysclk ns t slh last sck edge to miso change ? (ckpha = 1 only) 6 x t sysclk 8 x t sysclk ns note: t sysclk is equal to one per iod of the device syst em clock (sysclk). c8051t620/621/320/321/322/323 240 rev. 1.1 28. timers each mcu includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer fo r use with the smbus or for general purpose use. these timers can be used to measure time intervals, count external events and generate periodic interrupt requests. timer 0 and timer 1 are nearly identical and have four primary modes of operation. timer 2 and timer 3 offer 16-bit and split 8-bit timer functionality wi th auto-reload. additionally, timer 3 offers the ability to be clocked from the external oscillator while the device is in suspend mode, and can be used as a wake-up source. this allows for implementation of a very low-power system, including rtc capability. timers 0 and 1 may be clocked by one of five sour ces, determined by the timer mode select bits (t1m ? t0m) and the clock scale bits (sca1 ? sca0). the clock scale bits define a pre-scaled clock from which timer 0 and/or timer 1 may be clocked (see sfr definition 28.1 for pre-scaled clock selection). timer 0/1 may then be configured to use this pre-sc aled clock signal or the system clock. timer 2 and timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided by 8. timer 0 and timer 1 may also be operated as counte rs. when functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (t0 or t1). events with a fre- quency of up to one-fourth the system clock frequency can be counted. the input signal need not be peri- odic, but it should be held at a gi ven level for at least two full system cl ock cycles to ensure the level is properly sampled. timer 0 and timer 1 modes: ti mer 2 modes: timer 3 modes: 13-bit counter/timer 16-bit timer with auto-reload 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with auto- reload two 8-bit timers with auto-reload t wo 8-bit timers with auto-reload two 8-bit counter/timers (timer 0 only) rev. 1.1 241 c8051t620/621/320/321/322/323 sfr address = 0x8e sfr definition 28.1. ckcon: clock control bit76543210 name t3mh t3ml t2mh t2ml t1m t0m sca[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7t3mh timer 3 high byte clock select. selects the clock supplied to the timer 3 high byte (split 8-bit timer mode only). 0: timer 3 high byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 high byte uses the system clock. 6t3ml timer 3 low byte clock select. selects the clock supplied to timer 3. select s the clock supplied to the lower 8-bit timer in split 8-bit timer mode. 0: timer 3 low byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 low byte uses the system clock. 5t2mh timer 2 high byte clock select. selects the clock supplied to the timer 2 high byte (split 8-bit timer mode only). 0: timer 2 high byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. 4t2ml timer 2 low byte clock select. selects the clock supplied to timer 2. if timer 2 is configured in split 8-bit timer mode, this bit selects the clock supp lied to the lower 8-bit timer. 0: timer 2 low byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. 3t1 timer 1 clock select. selects the clock source supplied to timer 1. ignored when c/t1 is set to 1. 0: timer 1 uses the clock defined by the prescale bits sca[1:0]. 1: timer 1 uses the system clock. 2t0 timer 0 clock select. selects the clock source supplied to timer 0. ignored when c/t0 is set to 1. 0: counter/timer 0 uses the clock defi ned by the prescale bits sca[1:0]. 1: counter/timer 0 uses the system clock. 1:0 sca[1:0] timer 0/1 prescale bits. these bits control the timer 0/1 clock prescaler: 00: system clock divided by 12 01: system clock divided by 4 10: system clock divided by 48 11: external clock divided by 8 (synchronized with the system clock) c8051t620/621/320/321/322/323 242 rev. 1.1 28.1. timer 0 and timer 1 each timer is implemented as a 16-bit register acce ssed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer control register (tcon) is used to enable timer 0 and timer 1 as well as indicate status. timer 0 interrupts can be enabled by setting the et0 bit in the ie regis- ter (section ? note that the cpu is stalled during eprom write operations and usb fifo movx accesses (see section ?15.2.3. accessing usb fifo space? on page 88). interrup t service latency will be increased for interrupts occurring while the cpu is stalled. the latency for th ese situations will be determined by the standard interrupt service procedure (as described above ) and the amount of time the cpu is stalled.? on page 97); timer 1 interrupts can be enabled by setting the et1 bit in the ie register (section ? note that the cpu is stalled during eprom write operation s and usb fifo movx accesses (see section ?15.2.3. accessing usb fifo space? on page 88). inte rrupt service latency will be increased for interrupts occurring while the cp u is stalled. the latency for these situat ions will be determined by the standard interrupt service procedure (as described above) and the amount of time the cpu is stalled.? on page 97). both counter/timers operate in one of four primary modes selected by setting the mode select bits t1m1 ? t0m0 in the counter/timer mode register (tmod). ea ch timer can be configured independently. each operating mode is described below. 28.1.1. mode 0: 13 -bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration and operation of timer 0. however, both timers operate identically, and timer 1 is configured in the same manner as described for timer 0. the th0 register holds the eight msbs of the 13-bit c ounter/timer. tl0 holds the five lsbs in bit positions tl0.4 ? tl0.0. the three upper bits of tl0 (tl0.7 ? tl0.5) are indeterminate and should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf0 in tcon is set and an interrupt will occur if timer 0 interrupts are enabled. the c/t0 bit in the tmod register selects the counter/ timer's clock source. when c/t0 is set to logic 1, high-to-low transitions at the selected timer 0 input pi n (t0) increment the timer register (refer to section ?22.3. priority crossbar decoder? on page 137 for information on selecting and configuring external i/o pins). clearing c/t selects the clock defined by the t0 m bit in register ckcon. when t0m is set, timer 0 is clocked by the system clock. when t0m is cleared, timer 0 is clocked by the source selected by the clock scale bits in ckcon (see sfr definition 28.1). setting the tr0 bit (tcon.4) enables the timer when eit her gate0 in the tmod register is logic 0 or the input signal int0 is active as defined by bit in0pl in register it01cf (see sfr definition 17.7). setting gate0 to 1 allows the timer to be contro lled by the external input signal int0 (see section ? note that the cpu is stalled during eprom write operation s and usb fifo movx accesses (see section ?15.2.3. accessing usb fifo space? on page 88). inte rrupt service latency will be increased for interrupts occurring while the cp u is stalled. the latency for these situat ions will be determined by the standard interrupt service procedure (as described above) and the amount of time the cpu is stalled.? on page 97), facilitating pulse width measurements tr0 gate0 int0 counter/timer 0 x x disabled 1 0 x enabled 1 1 0 disabled 1 1 1 enabled note: x = don't care rev. 1.1 243 c8051t620/621/320/321/322/323 setting tr0 does not force the timer to reset. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is configured and controlled using the relevant tcon and tmod bits just as with timer 0. the input signal int1 is used with timer 1; the int1 polarity is defined by bit in1pl in register it01cf (see sfr definition 17.7). figure 28.1. t0 mode 0 block diagram 28.1.2. mode 1: 16 -bit counter/timer mode 1 operation is the same as mode 0, except that the counter/timer registers use all 16 bits. the coun- ter/timers are enabled and configured in mode 1 in the same manner as for mode 0. 28.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8- bit counter/timers with auto matic reload of the start value. tl0 holds the count and th0 holds the reload va lue. when the counter in tl0 overflows from all ones to 0x00, the timer over flow flag tf0 in the tcon register is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts ar e enabled, an interr upt will occur when the tf0 flag is set. the reload value in th0 is not changed. tl0 must be initialized to the desired value before enabling the timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit (tcon.4) enables the timer when either gate0 in the tmod regi ster is logic 0 or when the input signal int0 is active as defined by bit in0pl in register it 01cf (see section ?17.3. int0 and int1 external interrupt sources? on page 105 for details on the external input signals int0 and int1 ). tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tr0 0 1 0 1 sysclk pre-scaled clock tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 int0 t0 crossbar it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 in0pl xor t0m c8051t620/621/320/321/322/323 244 rev. 1.1 figure 28.2. t0 mode 2 block diagram 28.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8-bit counter/timers held in tl0 and th0. the coun- ter/timer in tl0 is controlled using the timer 0 control/status bits in tcon and tmod: tr0, c/t0, gate0 and tf0. tl0 can use either the system clock or an ex ternal input signal as its timebase. the th0 register is restricted to a timer function so urced by the system clock or presca led clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 ov erflow flag tf1 on overflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is operat ing in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud ra tes or overflow conditions for other peripherals. while timer 0 is operating in mode 3, timer 1 run control is handled through its mode settings. to run timer 1 while timer 0 is in mode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, configure it for mode 3. tclk tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) 0 1 0 1 sysclk pre-scaled clock it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 tr0 gate0 in0pl xor int0 t0 crossbar t0m rev. 1.1 245 c8051t620/621/320/321/322/323 figure 28.3. t0 mode 3 block diagram tl0 (8 bits) tmod 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt 0 1 sysclk pre-scaled clock tr1 th0 (8 bits) t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr0 gate0 in0pl xor int0 t0 crossbar t0m c8051t620/621/320/321/322/323 246 rev. 1.1 sfr address = 0x88; bit-addressable sfr definition 28.2. tcon: timer control bit76543210 name tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 tf1 timer 1 overflow flag. set to 1 by hardware when timer 1 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 1 interrupt service routine. 6tr1 timer 1 run control. timer 1 is enabled by setting this bit to 1. 5 tf0 timer 0 overflow flag. set to 1 by hardware when timer 0 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 0 interrupt service routine. 4tr0 timer 0 run control. timer 0 is enabled by setting this bit to 1. 3ie1 external interrupt 1. this flag is set by hardware when an edge/l evel of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 1 service routine in edge-triggered mode. 2it1 interrupt 1 type select. this bit selects whether the configured int1 interrupt will be edge or level sensitive. int1 is configured active low or high by the in1pl bit in the it01cf register (see sfr definition 17.7). 0: int1 is level triggered. 1: int1 is edge triggered. 1ie0 external interrupt 0. this flag is set by hardware when an edge/l evel of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 0 service routine in edge-triggered mode. 0it0 interrupt 0 type select. this bit selects whether the configured int0 interrupt will be edge or level sensitive. int0 is configured active low or high by the in0pl bit in register it01cf (see sfr definition 17.7). 0: int0 is level triggered. 1: int0 is edge triggered. rev. 1.1 247 c8051t620/621/320/321/322/323 sfr address = 0x89 sfr definition 28.3. tmod: timer mode bit76543210 name gate1 c/t1 t1m[1:0] gate0 c/t0 t0m[1:0] type r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7gate1 timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of int1 logic level. 1: timer 1 enabled only when tr1 = 1 and int1 is active as defined by bit in1pl in register it01cf (see sfr definition 17.7). 6c/t1 counter/timer 1 select. 0: timer: timer 1 incremented by clock defined by t1m bit in register ckcon. 1: counter: timer 1 incremented by high -to-low transitions on external pin (t1). 5:4 t1m[1:0] timer 1 mode select. these bits select the timer 1 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, timer 1 inactive 3gate0 timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of int0 logic level. 1: timer 0 enabled only when tr0 = 1 and int0 is active as defined by bit in0pl in register it01cf (see sfr definition 17.7). 2c/t0 counter/timer 0 select. 0: timer: timer 0 incremented by clock defined by t0m bit in register ckcon. 1: counter: timer 0 incremented by high -to-low transitions on external pin (t0). 1:0 t0m[1:0] timer 0 mode select. these bits select the timer 0 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, two 8-bit counter/timers c8051t620/621/320/321/322/323 248 rev. 1.1 sfr address = 0x8a sfr address = 0x8b sfr definition 28.4. tl0: timer 0 low byte bit76543210 name tl0[7:0] type r/w reset 00000000 bit name function 7:0 tl0[7:0] timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0. sfr definition 28.5. tl1: timer 1 low byte bit76543210 name tl1[7:0] type r/w reset 00000000 bit name function 7:0 tl1[7:0] timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1. rev. 1.1 249 c8051t620/621/320/321/322/323 sfr address = 0x8c sfr address = 0x8d sfr definition 28.6. th 0: timer 0 high byte bit76543210 name th0[7:0] type r/w reset 00000000 bit name function 7:0 th0[7:0] timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. sfr definition 28.7. th 1: timer 1 high byte bit76543210 name th1[7:0] type r/w reset 00000000 bit name function 7:0 th1[7:0] timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1. c8051t620/621/320/321/322/323 250 rev. 1.1 28.2. timer 2 timer 2 is a 16-bit timer formed by two 8-bit sfrs: tmr2l (low byte) and tmr2h (high byte). timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t2split bit (tmr2cn.3) defines the timer 2 operation mode. timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives the system clock while timer 2 (and/or the pca) is clocked by an external preci- sion oscillator. note that the external oscillator source divided by 8 is synchronized wi th the sys tem clock. 28.2.1. 16-bit time r with auto-reload when t2split (tmr2cn.3) is zero, timer 2 operates as a 16-bit timer with auto-reload. timer 2 can be clocked by sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-b it value in the timer 2 reload registers (tmr2rlh and tmr2rll) is loaded into the timer 2 register as shown in figure 28.4, and the timer 2 high byte overflow flag (tmr2cn.7) is set. if timer 2 interrupts are enabled (if ie.5 is set), an interrupt will be generated on each timer 2 overflow. additionally , if timer 2 interrupts are enabled and the tf2len bit is set (tmr2cn.5) , an interrupt will be generated each time the lower 8 bits (tmr2l) overflow from 0xff to 0x00. figure 28.4. timer 2 16-bit mode block diagram external clock / 8 sysclk / 12 sysclk tmr2l tmr2h tmr2rll tmr2rlh reload tclk 0 1 tr2 tmr2cn t2split tf2cen tf2l tf2h t2xclk tr2 0 1 t2xclk interrupt tf2len to adc, smbus to smbus tl2 overflow ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m rev. 1.1 251 c8051t620/621/320/321/322/323 28.2.2. 8-bit timers with auto-reload when t2split is set, timer 2 operates as two 8-bi t timers (tmr2h and tmr2l). both 8-bit timers oper- ate in auto-reload mode as shown in figure 28.5. tmr2rll holds the reload value for tmr2l; tmr2rlh holds the reload value for tmr2h. the tr2 bit in tmr2cn handles the run control for tmr2h. tmr2l is always running when configured for 8-bit mode. each 8-bit timer may be configured to use sysclk, sys clk divided by 12, or the external oscillator clock source divided by 8. the timer 2 clock select bits (t2mh and t2ml in ckcon) select either sysclk or the clock defined by the timer 2 external cloc k select bit (t2xclk in tmr2cn), as follows: the tf2h bit is set when tmr2h overflows from 0xff to 0x00; the tf2l bit is set when tmr2l overflows from 0xff to 0x00. when timer 2 interrupts are enabled (ie.5), an interrupt is generated each time tmr2h overflows. if timer 2 interrupts are enabled an d tf2len (tmr2cn.5) is set, an interrupt is gener- ated each time either tmr2l or tmr2h overflows. when tf2len is enabled, software must check the tf2h and tf2l flags to determine the source of the timer 2 interrupt. the tf2h and tf2l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 28.5. timer 2 8-bit mode block diagram t2mh t2xclk tmr2h clock source t2ml t2xclk tmr2l clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr2 external clock / 8 sysclk / 12 0 1 t2xclk 1 0 tmr2h tmr2rlh reload reload tclk tmr2l tmr2rll interrupt tmr2cn t2split tf2cen tf2len tf2l tf2h t2xclk tr2 to adc, smbus to smbus ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m c8051t620/621/320/321/322/323 252 rev. 1.1 28.2.3. low-frequency oscillator (lfo) capture mode the low-frequency oscillator capture mode allows the lfo clock to be measured against the system clock or an external oscillator so urce. timer 2 can be clocked from t he system clock, the system clock divided by 12, or the external oscillator divided by 8, depending on the t2ml (ckcon.4), and t2xclk settings. setting tf2cen to 1 enables the lfo capture mode for timer 2. in this mode, t2split should be set to 0, as the full 16-bit timer is used. upon a falling edge of the low-frequency oscillator, the contents of timer 2 (tmr2h:tmr2l) are loaded into the timer 2 rel oad registers (tmr2rlh:tmr2rll) and the tf2h flag is set. by recording the difference between two su ccessive timer capture valu es, the lfo clock frequency can be determined with respect to the timer 2 clock. the timer 2 clock should be much faster than the lfo to achieve an accurate reading. figure 28.6. timer 2 low-frequency oscillation capture mode block diagram external clock / 8 sysclk / 12 sysclk 0 1 0 1 t2xclk ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr2l tmr2h tclk tr2 tmr2rll tmr2rlh capture low-frequency oscillator tmr2cn t2split tf2cen tf2l tf2h t2xclk tr2 tf2len tf2cen interrupt rev. 1.1 253 c8051t620/621/320/321/322/323 sfr address = 0xc8; bit-addressable sfr definition 28.8. tm r2cn: timer 2 control bit76543210 name tf2h tf2l tf2len tf2cen t2split tr2 t2xclk type r/w r/w r/w r/w r/w r/w r r/w reset 00000000 bit name function 7 tf2h timer 2 high byte overflow flag. set by hardware when the timer 2 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 2 overflows from 0x ffff to 0x0000. when the timer 2 interrupt is enabled, setting this bit causes the cpu to vector to the timer 2 interrupt service routine. this bit is not automatically cleared by hardware. 6 tf2l timer 2 low byte overflow flag. set by hardware when the timer 2 low byte overflows from 0xff to 0x00. tf2l will be set when the low byte overflows regardless of the timer 2 mode. this bit is not automatically cleared by hardware. 5 tf2len timer 2 low byte interrupt enable. when set to 1, this bit enables timer 2 lo w byte interrupts. if ti mer 2 interrupts are also enabled, an interrupt will be generat ed when the low byte of timer 2 overflows. 4tf2cen timer 2 low-frequency oscillator capture enable. when set to 1, this bit enables timer 2 low-frequency oscillato r capture mode. if tf2cen is set and timer 2 interrupts are ena bled, an interrupt w ill be generated on a falling edge of the low-frequ ency oscillator output, an d the current 16-bit timer value in tmr2h:tmr2l will be copied to tmr2rlh:tmr2rll. 3 t2split timer 2 split mode enable. when this bit is set, timer 2 operates as two 8-bit timers with auto-reload. 0: timer 2 operates in 16-bit auto-reload mode. 1: timer 2 operates as two 8-bit auto-reload timers. 2tr2 timer 2 run control. timer 2 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/disables tmr2h only; tmr2l is alwa ys enabled in split mode. 1 unused unused. read = 0b; write = don?t care 0t2xclk timer 2 external clock select. this bit selects the external clock source for timer 2. if timer 2 is in 8-bit mode, this bit selects the external oscillator clock so urce for both timer bytes. however, the timer 2 clock select bits (t2mh and t2ml in register ckcon) may still be used to select between the external clock an d the system clock for either timer. 0: timer 2 clock is the system clock divided by 12. 1: timer 2 clock is the external clock divided by 8 (synchronized with sysclk). c8051t620/621/320/321/322/323 254 rev. 1.1 sfr address = 0xca sfr address = 0xcb sfr address = 0xcc sfr definition 28.9. tmr2rll: ti mer 2 reload register low byte bit76543210 name tmr2rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr2rll[7:0] timer 2 reload register low byte. tmr2rll holds the low byte of the reload value for timer 2. sfr definition 28.10. tmr2rlh: ti mer 2 reload register high byte bit76543210 name tmr2rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr2rlh[7:0] timer 2 reload register high byte. tmr2rlh holds the high byte of the reload value for timer 2. sfr definition 28.11. tm r2l: timer 2 low byte bit76543210 name tmr2l[7:0] type r/w reset 00000000 bit name function 7:0 tmr2l[7:0] timer 2 low byte. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8- bit mode, tmr2l contains the 8-bit low byte timer value. rev. 1.1 255 c8051t620/621/320/321/322/323 sfr address = 0xcd sfr definition 28.12. tmr2h timer 2 high byte bit76543210 name tmr2h[7:0] type r/w reset 00000000 bit name function 7:0 tmr2h[7:0] timer 2 low byte. in 16-bit mode, the tmr2h register contains the high byte of the 16-bit timer 2. in 8- bit mode, tmr2h contains the 8-bit high byte timer value. c8051t620/621/320/321/322/323 256 rev. 1.1 28.3. timer 3 timer 3 is a 16-bit timer formed by two 8-bit sfrs: tmr3l (low byte) and tmr3h (high byte). timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t3split bit (tmr3cn.3) defines the timer 3 operation mode. timer 3 may be clocked by the system clock, the system clock divided by 12, the exte rnal oscillator source divided by 8, or the internal low-frequency oscillator di vided by 8. the external clock mode is ideal for real- time clock (rtc) func tionality, where the internal high-frequency oscillator driv es the system clock while timer 3 is clocked by an ex ternal oscillator source. note that the external oscillator source divided by 8 and the lfo source divided by 8 are synchronized with th e system clock when in al l operating modes except suspend. when the internal oscillator is placed in suspend mode, the external clock/8 si gnal or the lfo/8 output can directly drive the timer. this allows the use of an external clock or the lfo to wake up the device from suspend mode. the timer will continue to run in suspen d mode and count up. when the timer overflow occurs, the device will wake from suspen d mode, and begin executing code again. the timer value may be set prior to entering suspend, to overflow in the desired amount of time (number of clocks) to wake the device. if a wake-up source other than t he timer wakes the device from suspend mode, it may take up to three timer clocks before the timer regist ers can be read or written. during this time, the stsync bit in register oscicn will be set to 1, to indicate that it is not safe to read or write the timer reg- isters. important note: in internal lfo/8 mode, the divider for the internal lfo must be set to 1 for proper func- tionality. the timer will not operate if the lfo di vider is not set to 1. 28.3.1. 16-bit time r with auto-reload when t3split (tmr3cn.3) is zero, timer 3 operates as a 16-bit timer with auto-reload. timer 3 can be clocked by sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 3 reload registers (tmr3rlh and tmr3rll) is loaded in to the timer 3 register as shown in figure 28.7, and the timer 3 high byte overflow fl ag (tmr3cn.7) is set. if timer 3 interrupts are enabled (if eie1.7 is set), an interrupt will be gener ated on each timer 3 overflow. addition ally, if timer 3 inte rrupts are enabled and the tf3len bit is set (tmr3cn.5) , an interrupt will be generated each time the lower 8 bits (tmr3l) overflow from 0xff to 0x00. figure 28.7. timer 3 16-bit mode block diagram sysclk tmr3l tmr3h tmr3rll tmr3rlh reload tclk 0 1 tr3 tmr3cn t3split t3xclk1 tf3cen tf3l tf3h t3xclk0 tr3 interrupt tf3len to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m external clock / 8 sysclk / 12 00 t3xclk[1:0] 01 11 internal lfo / 8 rev. 1.1 257 c8051t620/621/320/321/322/323 28.3.2. 8-bit timers with auto-reload when t3split is set, timer 3 operates as two 8-bi t timers (tmr3h and tmr3l). both 8-bit timers oper- ate in auto-reload mode as shown in figure 28.8. tmr3rll holds the reload value for tmr3l; tmr3rlh holds the reload value for tmr3h. the tr3 bit in tmr3cn handles the run control for tmr3h. tmr3l is always running when configured for 8-bit mode. each 8-bit timer may be configured to use sysclk, sysclk divided by 12 , the external oscillator clock source divided by 8, or the intern al low-frequency oscilla tor. the timer 3 clock select bits (t3mh and t3ml in ckcon) select either sysclk or the clock defined by the timer 3 external clock select bits (t3xclk[1:0] in tmr3cn), as follows: the tf3h bit is set when tmr3h overflows from 0xff to 0x00; the tf3l bit is set when tmr3l overflows from 0xff to 0x00. when timer 3 interrupts are enabled, an interrupt is generated each time tmr3h over- flows. if timer 3 interrupts are enabled and tf3len (tmr3cn.5) is set, an interrupt is generated each time either tmr3l or tmr3h overflows. when tf3le n is enabled, software must check the tf3h and tf3l flags to determine the source of the timer 3 interrupt. the tf3h and tf3l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 28.8. timer 3 8-bit mode block diagram t3mh t3xclk[1:0] tmr3h clock source t3ml t3xclk[1:0] tmr3l clock source 0 00 sysclk / 12 0 00 sysclk / 12 0 01 external clock / 8 0 01 external clock / 8 0 10 reserved 0 10 reserved 0 11 internal lfo 0 11 internal lfo 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr3 1 0 tmr3h tmr3rlh reload reload tclk tmr3l tmr3rll interrupt tmr3cn t3split t3xclk1 tf3cen tf3len tf3l tf3h t3xclk0 tr3 to adc external clock / 8 sysclk / 12 00 t3xclk[1:0] 01 11 internal lfo / 8 ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m c8051t620/621/320/321/322/323 258 rev. 1.1 28.3.3. low-frequency oscillator (lfo) capture mode the low-frequency oscillator capture mode allows the lfo clock to be measured against the system clock or an external oscillator so urce. timer 3 can be clocked from t he system clock, the system clock divided by 12, or the external oscillator divide d by 8, depending on th e t3ml (ckcon.6), and t3xclk[1:0] settings. setting tf3cen to 1 enables the lfo capture mode for timer 3. in this mode, t3split should be set to 0, as the full 16-bit time r is used. upon a falling e dge of the low-frequency o scillator, the contents of timer 3 (tmr3h:tmr3l) are loaded into the time r 3 reload registers (t mr3rlh:tmr3rll) and the tf3h flag is set. by recording the difference betw een two successive timer capture values, the lfo clock frequency can be determined with respect to the timer 3 clock. the timer 3 clock should be much faster than the lfo to achieve an accurate reading. this means that the lfo/8 should not be selected as the timer clock source in this mode. figure 28.9. timer 3 low-frequency oscillation capture mode block diagram external clock / 8 sysclk / 12 sysclk 0 1 00 01 t3xclk[1:0] ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr3l tmr3h tclk tr3 tmr3rll tmr3rlh capture low-frequency oscillator tmr3cn t3split t3xclk1 tf3cen tf3l tf3h t3xclk0 tr3 tf3len tf3cen interrupt rev. 1.1 259 c8051t620/621/320/321/322/323 sfr address = 0x91 sfr definition 28.13. tm r3cn: timer 3 control bit76543210 name tf3h tf3l tf3len tf3cen t3split tr3 t3xclk[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 tf3h timer 3 high byte overflow flag. set by hardware when the timer 3 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 3 overflows from 0x ffff to 0x0000. when the timer 3 interrupt is enabled, setting this bit causes the cpu to vector to the timer 3 interrupt service routine. this bit is not automatica lly cleared by hardware. 6 tf3l timer 3 low byte overflow flag. set by hardware when the timer 3 low byte overflows from 0xff to 0x00. tf3l will be set when the low byte overflows regardless of the timer 3 mode. this bit is not automatically cleared by hardware. 5 tf3len timer 3 low byte interrupt enable. when set to 1, this bit enables timer 3 lo w byte interrupts. if ti mer 3 interrupts are also enabled, an interrupt will be generat ed when the low byte of timer 3 overflows. 4tf3cen timer 3 low-frequency oscillator capture enable. when set to 1, this bit enables timer 3 low-frequency oscillato r capture mode. if tf3cen is set and timer 3 interrupts are enabled, an interrupt will be generated on a falling edge of the low-frequ ency oscillator output, an d the current 16-bit timer value in tmr3h:tmr3l will be copied to tmr3rlh:tmr3rll. 3 t3split timer 3 split mode enable. when this bit is set, timer 3 operates as two 8-bit timers with auto-reload. 0: timer 3 operates in 16-bit auto-reload mode. 1: timer 3 operates as two 8-bit auto-reload timers. 2tr3 timer 3 run control. timer 3 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/disables tmr3h only; tmr3l is alwa ys enabled in split mode. 1:0 t3xclk[1:0] timer 3 external clock select. this bit selects the ?external? clock source for timer 3. if timer 3 is in 8-bit mode, this bit selects the external oscillator clock source for both timer bytes. however, the timer 3 clock select bits (t3mh and t3ml in register ckcon) may still be used to select between the external clock an d the system clock for either timer. 00: system clock divided by 12. 01: external cl ock divided by 8 (synchronized with sysclk when not in suspend). 10: reserved. 11: internal lfo/8 (synchronized with sysclk when not in suspend). c8051t620/621/320/321/322/323 260 rev. 1.1 sfr address = 0x92 sfr address = 0x93 sfr address = 0x94 sfr definition 28.14. tmr3rll: ti mer 3 reload register low byte bit76543210 name tmr3rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr3rll[7:0] timer 3 reload register low byte. tmr3rll holds the low byte of the reload value for timer 3. sfr definition 28.15. tmr3rlh: ti mer 3 reload register high byte bit76543210 name tmr3rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr3rlh[7:0] timer 3 reload register high byte. tmr3rlh holds the high byte of the reload value for timer 3. sfr definition 28.16. tm r3l: timer 3 low byte bit76543210 name tmr3l[7:0] type r/w reset 00000000 bit name function 7:0 tmr3l[7:0] timer 3 low byte. in 16-bit mode, the tmr3l register contains the low byte of the 16-bit timer 3. in 8-bit mode, tmr3l contains the 8-bit low byte timer value. rev. 1.1 261 c8051t620/621/320/321/322/323 sfr address = 0x95 sfr definition 28.17. tmr3h timer 3 high byte bit76543210 name tmr3h[7:0] type r/w reset 00000000 bit name function 7:0 tmr3h[7:0] timer 3 high byte. in 16-bit mode, the tmr3h register contains the high byte of the 16-bit timer 3. in 8-bit mode, tmr3h contains the 8-bit high byte timer value. c8051t620/621/320/321/322/323 262 rev. 1.1 29. programmable counter array the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. th e pca consists of a dedicated 16-bit counter/timer and five 16-bit capture/compare modules. each capture/compare module has its own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled. the counter/timer is driven by a programmable timebase that can select between six sources: system clo ck, system clock divided by four, system clock divided by twelve , the external oscillator clock source di vided by 8, timer 0 overflows, or an external clock signal on the eci input pin. each capture/compare module may be configured to operate independently in one of six modes: edge-triggered capture, software timer, high-speed output, fre- quency output, 8 to 11-bit pwm, or 16-bit pwm (each mode is described in section ?29.3. capture/compare modules? on page 265). the external oscillator clock option is ideal for real-time clock (rtc) functionality, allowing the pca to be cloc ked by a precision external oscillator while the inter- nal oscillator drives the sys tem clock. the pca is conf igured and controlled throug h the system controller's special function registers. the pca bl ock diagram is shown in figure 29.1. important note: the pca module 4 may be used as a watchdog timer (wdt), and is enabled in this mode following a system reset. access to certain pca registers is restricted while wdt mode is enabled . see section 29.4 for details. figure 29.1. pca block diagram 16-bit counter/timer cex1 eci digital crossbar cex2 cex0 port i/o capture/compare module 1 capture/compare module 0 capture/compare module 2 pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 capture/compare module 3 cex3 capture/compare module 4 / wdt cex4 rev. 1.1 263 c8051t620/621/320/321/322/323 29.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bi t sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the low byte (lsb). reading pca0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesses this ?snapshot? register. reading the pca0l register first guarantees an accu rate reading of the entire 16-bit pca0 counter. reading pca0h or pca0l does not disturb the counter operation. the cps2 ? cps0 bits in the pca0md register select the timebase for the counter/timer as shown in table 29.1. when the counter/timer overflows from 0xffff to 0x0 000, the counter overflow fl ag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the inte rrupt service routine, and must be cleared by soft- ware. clearing the cidl bit in the pca0md register a llows the pca to continue normal operation while the cpu is in idle mode. table 29.1. pca timebase input options cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 0 1 1 high-to-low transitions on eci (max rate = system clock divided by 4) 100system clock 1 0 1 external oscillator source divided by 8 * 1 1 x reserved. note: external oscillator source divided by 8 is synchronized with the system clock. c8051t620/621/320/321/322/323 264 rev. 1.1 figure 29.2. pca counter/timer block diagram 29.2. pca0 interrupt sources figure 29.3 shows a diagram of the pca interrupt tree. there are five independent event flags that can be used to generate a pca0 interrupt. they are: the main pca counter overflow flag (cf), which is set upon a 16-bit overflow of the pca0 counter, an intermediate overflow flag (covf), which can be set on an over- flow from the 8th, 9th, 10th, or 11th bit of the pca0 counter, and the individual flags for each pca channel (ccf0, ccf1, ccf2, ccf3, and ccf4), which are set according to the operation mode of that module. these event flags are always set when the trigger condit ion occurs. each of these flags can be individually selected to generate a pca0 interrupt, using the co rresponding interrupt enable flag (ecf for cf, ecov for covf, and eccfn for each ccfn). pca0 interrupts must be globally enabled before any individual interrupt sources are recognized by the processor. pc a0 interrupts are globally enabled by setting the ea bit and the epca0 bit to logic 1. pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 idle 0 1 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 100 101 sysclk external clock/8 rev. 1.1 265 c8051t620/621/320/321/322/323 figure 29.3. pca interrupt block diagram 29.3. capture/compare modules each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high speed output, frequency output, 8 to 11-bit pulse width modulator, or 16- bit pulse width modulator. each module has special func tion registers (sfrs) associated with it in the cip-51 system controller. these registers are used to exchange data with a module and configure the module's mode of operation. table 29.2 summariz es the bit settings in the pca0cpmn and pca0pwm registers used to select the pca capture/compare modu le?s operating mode. note that all modules set to use 8, 9, 10, or 11-bit pwm mode must use the same cycle length (8-11 bits). setting the eccfn bit in a pca0cpmn register enables the module's ccfn interrupt. pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 0 1 pca module 0 (ccf0) pca module 1 (ccf1) eccf1 0 1 eccf0 0 1 pca module 2 (ccf2) eccf2 pca counter/timer 16- bit overflow 0 1 interrupt priority decoder epca0 0 1 ea 0 1 pca0cpmn (for n = 0 to 4) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0pwm a r s e l e c o v c l s e l 0 c l s e l 1 c o v f pca counter/timer 8, 9, 10 or 11-bit overflow 0 1 set 8, 9, 10, or 11 bit operation 0 1 pca module 3 (ccf3) eccf3 0 1 pca module 4 (ccf4) eccf4 c8051t620/621/320/321/322/323 266 rev. 1.1 29.3.1. edge-triggered capture mode in this mode, a valid transition on the cexn pin ca uses the pca to capture the value of the pca coun- ter/timer and load it into the corresponding module 's 16-bit capture/compare register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transi- tion that triggers the capture: low-to-high transition (p ositive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an in terrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt ser- vice routine, and must be cleared by software. if both cappn and capnn bits are set to l ogic 1, then the state of the port pin associated with cexn can be read directly to determine whether a rising-edge or fall- ing-edge caused the capture. table 29.2. pca0cpm and pca0pwm bit settings for pca capture/compare modules operational mode pca0cpmn pca0pwm bit number 765432107654-2 1-0 capture triggered by positive edge on cexn xx10000a0xbxxxxx capture triggered by negative edge on cexn xx01000a0xbxxxxx capture triggered by any transition on cexn xx11000a0xbxxxxx software timer xc00100a0xbxxxxx high speed output xc00110a0xbxxxxx frequency output xc00011a0xbxxxxx 8-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a 0 x b xxx 00 9-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 01 10-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 10 11-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 11 16-bit pulse width modulator 1 c 0 0 e 0 1 a 0 x b xxx xx 1. x = don?t care (no functional difference for individual module if 1 or 0). 2. a = enable interrupts for this module (pca interrupt triggered on ccfn set to 1). 3. b = enable 8th, 9th, 10th or 11th bit overflow interrupt (depends on setting of clsel[1:0]). 4. c = when set to 0, the digital comparator is off. for high speed and frequency output modes, the associated pin will not toggle. in any of the pwm modes, this gener ates a 0% duty cycle (output = 0). 5. d = selects whether the capture/compare register (0) or the auto-reload register (1) for the associated channel is accessed via addresses pca0cphn and pca0cpln. 6. e = when set, a match event will cause the ccfn flag for the associated channel to be set. 7. all modules set to 8, 9, 10 or 11-bit pwm mode use the same cycle length setting. rev. 1.1 267 c8051t620/621/320/321/322/323 figure 29.4. pca capture mode diagram note: the cexn input sign al must remain high or lo w for at least 2 system clock cycles to be recognized by the hardware. 29.3.2. software timer (compare) mode in software timer mode, the pca counter/timer value is compared to the module's 16-bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt ser- vice routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn regis- ter enables software timer mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt x 000x x c8051t620/621/320/321/322/323 268 rev. 1.1 figure 29.5. pca software timer mode diagram 29.3.3. high-speed output mode in high-speed output mode, a module?s associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16- bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if th e ccfn interrupt for that module is enabled. the ccfn bit is not auto- matically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by software. setting the togn, matn, and ecomn bi ts in the pca0cpmn register enables the high- speed output mode. if ecomn is cleare d, the associated pin will retain it s state, and not toggle on the next match event. i mportant note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt rev. 1.1 269 c8051t620/621/320/321/322/323 figure 29.6. pca high-speed output mode diagram 29.3.4. frequency output mode frequency output mode produces a programmable-freq uency square wave on the module?s associated cexn pin. the capture/compare module high byte holds the number of pca clocks to count before the out- put is toggled. the frequency of the square wave is then defined by equation 29.1. equation 29.1. square wave frequency output where f pca is the frequency of the clock selected by the cps2 ? 0 bits in the pca mode register, pca0md. the lower byte of the capture/compare modu le is compared to the pca counter low byte; on a match, cexn is toggled and the offset held in the hi gh byte is added to the matched value in pca0cpln. frequency output mode is enabled by setting the ecomn, togn, and pwmn bits in the pca0cpmn reg- ister. note that the matn bit should normally be set to 0 in this mode. if the matn bit is set to 1, the ccfn flag for the channel will be set when the 16-bit pca0 co unter and the 16-bit capture/comp are register for the channel are equal. match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt f cexn f pca 2 pca0 cphn ? ------------------- --------------------- - = note: a value of 0x00 in the pca0cphn register is equal to 256 for this equation. c8051t620/621/320/321/322/323 270 rev. 1.1 figure 29.7. pca frequency output mode 29.3.5. 8-bit, 9-bit, 10-bit and 11-bit pulse width modulator modes each module can be used independently to generate a pulse width modulated (pwm) output on its associ- ated cexn pin. the frequency of the output is depe ndent on the timebase for the pca counter/timer, and the setting of the pwm cycle length (8, 9, 10 or 11-bits). for backwar ds-compatibility wi th the 8-bit pwm mode available on other devices, the 8-bit pwm mode operates slightly differen t than 9, 10 and 11-bit pwm modes. it is important to note that all channels configured for 8/9/10/11-bit pwm mode will use the same cycle length. it is not possible to configure one channel for 8-bit pwm mode and another for 11- bit mode (for example). however, other pca channels can be configured to pin capture, high-speed out- put, software timer, frequency output, or 16-bit pwm mode independently. 29.3.5.1. 8-bit puls e width modulator mode the duty cycle of the pwm output signal in 8-bit pwm mode is varied using the module's pca0cpln cap- ture/compare register. when the value in the low byte of the pca counter/timer (pca0l) is equal to the value in pca0cpln, the output on th e cexn pin will be set. when the co unt value in pca0l overflows, the cexn output will be reset (see figu re 29.8). also, when th e counter/timer lo w byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded automatically with the value stored in the module?s capture/compare high byte (pca0cphn) without software intervention. setting the ecomn and pwmn bits in the pca0cpmn register, and setting the clsel bits in register pca0pwm to 00b enables 8-bit pulse width modulator mode. if the matn bit is set to 1, the ccfn flag for the modu le will be set each time an 8-bit comparator match (rising edge) occurs. the covf flag in pca0pwm can be used to detect the overflow (falling edge), which will occur every 256 pca clock cycles. the duty cycle for 8-bit pwm mode is given in equation 29.2. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 29.2. 8-bit pwm duty cycle using equation 29.2, the largest duty cycle is 100 % (pca0cphn = 0), and the smallest duty cycle is 0.39% (pca0cphn = 0xff). a 0% duty cycle may be generated by clearing the ecomn bit to 0. 8-bit comparator pca0l enable pca timebase match pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 000 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x enb enb 0 1 write to pca0cpln write to pca0cphn reset duty cycle 256 pca0 cphn ? ?? 256 ----------------------------------- ---------------- = rev. 1.1 271 c8051t620/621/320/321/322/323 figure 29.8. pca 8-bit pwm mode diagram 29.3.5.2. 9/10/1 1-bit pulse width modulator mode the duty cycle of the pwm output signa l in 9/10/11-bit pwm mode should be varied by writing to an ?auto- reload? register, which is dual-mapped into the pc a0cphn and pca0cpln register locations. the data written to define the duty cycle should be right-just ified in the registers. the auto-reload registers are accessed (read or written) when the bit arsel in pca0pwm is set to 1. the capture/compare registers are accessed when arsel is set to 0. when the least-significant n bits of the pca0 coun ter match the value in the associated module?s cap- ture/compare register (pca0cpn), the output on cexn is asserted high. when the counter overflows from the nth bit, cexn is asserted low (see figure 29.9). up on an overflow from the nth bit, the covf flag is set, and the value stored in the module?s auto-reload r egister is loaded into the capture/compare register. the value of n is determined by the clsel bits in register pca0pwm. the 9, 10 or 11-bit pwm mode is selected by setting the ecomn and pwmn bits in the pca0cpmn regis- ter, and setting the clsel bits in register pca0pwm to the desired cycle length (other than 8-bits). if the matn bit is set to 1, the ccfn flag for the module will be set each ti me a comparator match (rising edge) occurs. the covf flag in pca0pwm can be used to detect the overflow (falling edge), which will occur every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) pca clock cycles . the duty cycle for 9/10/11-bit pwm mode is given in equation 29.2, where n is the number of bits in the pwm cycle. important note about pca0cphn and pca0cpln registers : when writing a 16-bit value to the pca0cpn registers, the low byte should always be wr itten first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 29.3. 9, 10, and 11-bit pwm duty cycle 8-bit comparator pca0l pca0cpln pca0cphn cexn crossbar port i/o enable overflow pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 pca0pwm a r s e l e c o v c l s e l 0 c l s e l 1 c o v f x0 0 0 enb enb 0 1 write to pca0cpln write to pca0cphn reset covf duty cycle 2 n pca0 cpn ? ?? n -------------------------------- ----------- - = c8051t620/621/320/321/322/323 272 rev. 1.1 a 0% duty cycle may be generated by clearing the ecomn bit to 0. figure 29.9. pca 9, 10 and 11-bit pwm mode diagram 29.3.6. 16-bit pulse width modulator mode a pca module may also be operated in 16-bit pwm mode. 16-bit pwm mode is independent of the other (8/9/10/11-bit) pwm modes. in this mode, the 16-bit capture/compare module defines the number of pca clocks for the low time of the pwm signal. when the pca counter matches the module contents, the out- put on cexn is asserted high; when the 16-bit counter overflows, cexn is asserted low. to output a vary- ing duty cycle, new value writes should be synchronized with pca ccfn match interrupts. 16-bit pwm mode is enabled by setting the ecomn, pwmn, and pw m16n bits in the pca0cpmn register. for a vary- ing duty cycle, match interrupts should be enabled (eccfn = 1 and matn = 1) to help synchronize the capture/comp are register writes. if the matn bit is set to 1, the ccfn flag for the module will be set each time a 16-bit comparator match (rising edge) occurs. the cf flag in pca0cn can be used to detect the overflow (falling edge). the du ty cycle for 16-bit pwm mode is given by equation 29.4. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 29.4. 16-bit pwm duty cycle using equation 29.4, the largest duty cycle is 100% (pca0cpn = 0), and the smallest duty cycle is 0.0015% (pca0cpn = 0xffff). a 0% duty cycle may be generated by clearing the ecomn bit to 0. n-bit comparator pca0h:l (capture/compare) pca0cph:ln (right-justified) (auto-reload) pca0cph:ln (right-justified) cexn crossbar port i/o enable overflow of n th bit pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 pca0pwm a r s e l e c o v c l s e l 0 c l s e l 1 c o v f x enb enb 0 1 write to pca0cpln write to pca0cphn reset r/w when arsel = 1 r/w when arsel = 0 set ?n? bits: 01 = 9 bits 10 = 10 bits 11 = 11 bits duty cycle 65536 pca0 cpn ? ?? rev. 1.1 273 c8051t620/621/320/321/322/323 figure 29.10. pca 16-bit pwm mode 29.4. watchdog timer mode a programmable watchdog timer (wdt) function is avai lable through the pca module 4. the wdt is used to generate a reset if the time between writes to th e wdt update register (pca0cph4) exceed a specified limit. the wdt can be configured and enabled/disabled as needed by software. with the wdte bit set in the pca0md register, modu le 4 operates as a watchdog timer (wdt). the mod- ule 4 high byte is compared to the pca counter high byte; the module 4 low byte holds the offset to be used when wdt updates are performed. the watchdog timer is enabled on reset. writes to some pca registers are restricted while the watchdog timer is enabled. the wdt will generate a reset shortly after code begins execution. to avoid this re set, the wdt should be explicitly disabled (and option- ally re-configured and re-enabled if it is used in the system). 29.4.1. watchdog timer operation while the wdt is enabled: ? pca counter is forced on. ? writes to pca0l and pca0h are not allowed. ? pca clock source bits (cps2 ? cps0) are frozen. ? pca idle control bit (cidl) is frozen. ? module 4 is forced into software timer mode. ? writes to the module 4 mode register (pca0cpm4) are disabled. while the wdt is enabled, wr ites to the cr bit will not change the pca c ounter state; the counter will run until the wdt is disabled. the pca counter run co ntrol bit (cr) will read zero if the wdt is enabled but user software has not enabled th e pca counter. if a match occurs between pca0cph4 and pca0h while the wdt is enabled, a reset will be generated. to pr event a wdt reset, the wd t may be updated with a write of any value to pca0cph4. upon a pca0cph4 write, pca0h plus the offset held in pca0cpl4 is loaded into pca0cph4 (see figure 29.11). pca0cpln pca0cphn enable pca timebase 00x0 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 16-bit comparator cexn crossbar port i/o overflow q q set clr s r match pca0h pca0l enb enb 0 1 write to pca0cpln write to pca0cphn reset c8051t620/621/320/321/322/323 274 rev. 1.1 figure 29.11. pca module 2 with watchdog timer enabled note that the 8-bit offset held in pca0cph4 is comp ared to the upper byte of the 16-bit pca counter. this offset value is the number of pca0l overflows before a reset. up to 256 pca clocks may pass before the first pca0l overflow occurs, depending on the valu e of the pca0l when the update is performed. the total offset is then given (in pca clocks) by equation 29.5, where pca0l is the value of the pca0l register at the time of the update. equation 29.5. watchdog timer offset in pca clocks the wdt reset is generated when pca0l overflow s while there is a match between pca0cph4 and pca0h. software may force a wdt reset by writing a 1 to the ccf4 flag (pca0cn.4) while the wdt is enabled. 29.4.2. watchdog timer usage to configure the wdt, perform the following tasks: ? disable the wdt by writing a 0 to the wdte bit. ? select the desired pca cl ock source (with the cps2 ? cps0 bits). ? load pca0cpl4 with the desi red wdt update offset value. ? configure the pca idle mode (set cidl if the wd t should be suspended while the cpu is in idle mode). ? enable the wdt by setting the wdte bit to 1. ? reset the wdt timer by writing to pca0cph4. the pca clock source and idle mode select cannot be changed while the wdt is enabled. the watchdog timer is enabled by setting the wdte or wdlck bits in the pca0md register. when wdlck is set, the wdt cannot be disabled until the next system reset. if wdlck is not set, the wdt is disabled by clearing the wdte bit. the wdt is enabled following any reset. the pca0 c ounter clock defaults to the system clock divided by 12, pca0l defaults to 0x00, and pca0cpl4 defaults to 0x00. using equation 29.5, this results in a wdt pca0h enable pca0l overflow reset pca0cpl4 8-bit adder pca0cph4 adder enable pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 match write to pca0cph4 8-bit comparator offset 256 pca0 cpl4 u 256 pca0 l ? + = rev. 1.1 275 c8051t620/621/320/321/322/323 timeout interval of 256 pca clock cycles, or 3072 syste m clock cycles. table 29.3 lists some example time- out intervals for typical system clocks. 29.5. register d escriptions for pca0 following are detailed descriptions of the special function registers related to the operation of the pca. table 29.3. watchdog timer timeout intervals 1 system clock (hz) pca0cpl4 timeout interval (ms) 12,000,000 255 65.5 12,000,000 128 33.0 12,000,000 32 8.4 24,000,000 255 32.8 24,000,000 128 16.5 24,000,000 32 4.2 1,500,000 2 255 524.3 1,500,000 2 128 264.2 1,500,000 2 32 67.6 32,768 255 24,000 32,768 128 12,093.75 32,768 32 3,093.75 notes: 1. assumes sysclk/12 as the pca clock source, and a pca0l value of 0x00 at the update time. 2. internal sysclk reset frequency = internal oscillator divided by 8. c8051t620/621/320/321/322/323 276 rev. 1.1 sfr address = 0xd8; bit-addressable sfr definition 29.1. pca0cn: pca control bit76543210 name cf cr ccf4 ccf3 ccf2 ccf1 ccf0 type r/w r/w r r/w r/w r/w r/w r/w reset 00000000 bit name function 7cf pca counter/timer overflow flag. set by hardware when the pca counter/ timer overflows from 0xffff to 0x0000. when the counter/timer overflow (cf) interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service r outine. this bit is not automatically cleared by hardware and must be cleared by software. 6cr pca counter/timer run control. this bit enables/disables the pca counter/timer. 0: pca counter/timer disabled. 1: pca counter/timer enabled. 5 unused unused. read = 0b, write = don't care. 4 ccf4 pca module 4 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf4 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou- tine. this bit is not automatically cleared by hardware and must be cleared by software. 3 ccf3 pca module 3capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf3 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou- tine. this bit is not automatically cleared by hardware and must be cleared by software. 2 ccf2 pca module 2 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf2 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou- tine. this bit is not automatically cleared by hardware and must be cleared by software. 1 ccf1 pca module 1 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf1 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou- tine. this bit is not automatically cleared by hardware and must be cleared by software. 0 ccf0 pca module 0 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf0 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou- tine. this bit is not automatically cleared by hardware and must be cleared by software. rev. 1.1 277 c8051t620/621/320/321/322/323 sfr address = 0xd9 sfr definition 29.2 . pca0md: pca mode bit76543210 name cidl wdte wdlck cps2 cps1 cps0 ecf type r/w r/w r/w r r/w r/w r/w r/w reset 01000000 bit name function 7cidl pca counter/timer idle control. specifies pca behavior when cpu is in idle mode. 0: pca continues to function normally while the system co ntroller is in idle mode. 1: pca operation is suspended while th e system controller is in idle mode. 6wdte watchdog timer enable. if this bit is set, pca module 4 is used as the watchdog timer. 0: watchdog timer disabled. 1: pca module 4 enabled as watchdog timer. 5 wdlck watchdog timer lock. this bit locks/unlocks the watchdog timer e nable. when wdlck is set, the watchdog timer may not be disabled until the next system reset. 0: watchdog timer enable unlocked. 1: watchdog timer enable locked. 4 unused unused. read = 0b, write = don't care. 3:1 cps[2:0] pca counter/timer pulse select. these bits select the timebase source for the pca counter 000: system clock divided by 12 001: system clock divided by 4 010: timer 0 overflow 011: high-to-low transitions on eci (max rate = system clock divided by 4) 100: system clock 101: external clock divided by 8 (synchronized with the system clock) 11x: reserved 0ecf pca counter/timer overflow interrupt enable. this bit sets the masking of the pca co unter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca counter/timer overflow in terrupt request when cf (pca0cn.7) is set. note: when the wdte bit is set to 1, the other bits in the pca0md register cannot be modified. to change the contents of the pca0md register, the watchdog timer must first be disabled. c8051t620/621/320/321/322/323 278 rev. 1.1 sfr address = 0xf4 sfr definition 29.3. pca0pw m: pca pwm configuration bit76543210 name arsel ecov covf clsel[1:0] type r/w r/w r/w r r r r/w reset 00000000 bit name function 7arsel auto-reload register select. this bit selects whether to read and write the normal pca capture/compare registers (pca0cpn), or the auto-reload registers at the same sfr addresses. this function is used to define the reload value for 9, 10, and 11-bit pwm modes. in all other modes, the auto-reload registers have no function. 0: read/write capture/compare registers at pca0cphn and pca0cpln. 1: read/write auto-reload regi sters at pca0cphn and pca0cpln. 6ecov cycle overflow interrupt enable. this bit sets the masking of the cycle overflow flag (covf) interrupt. 0: covf will not gene rate pca interrupts. 1: a pca interrupt will be ge nerated when covf is set. 5covf cycle overflow flag. this bit indicates an overflow of the 8th, 9th, 10th, or 11th bit of the main pca counter (pca0). the specific bit used for this flag depends on the setting of the cycle length select bits. the bit can be set by hardware or software, but must be cleared by soft- ware. 0: no overflow has occurred since the last time this bit was cleared. 1: an overflow has occurred since t he last time this bit was cleared. 4:2 unused unused. read = 000b; write = don?t care. 1:0 clsel[1:0] cycle length select. when 16-bit pwm mode is not selected, th ese bits select the length of the pwm cycle, between 8, 9, 10, or 11 bits. this affects all channels configured for pwm which are not using 16-bit pwm mode. these bits ar e ignored for individual channels config- ured to16-bit pwm mode. 00: 8 bits. 01: 9 bits. 10: 10 bits. 11: 11 bits. rev. 1.1 279 c8051t620/621/320/321/322/323 sfr addresses: 0xda (n = 0), 0xdb (n = 1), 0xdc (n = 2), 0xdd (n = 3), 0xde (n = 4) sfr definition 29.4. pca0cpmn : pca capture/compare mode bit76543210 name pwm16n ecomn cappn capnn matn togn pwmn eccfn type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7pwm16n 16-bit pulse width modulation enable. this bit enables 16-bit mode when pulse width modulation mode is enabled. 0: 8 to 11-bit pwm selected. 1: 16-bit pwm selected. 6ecomn comparator function enable. this bit enables the comparator function for pca module n when set to 1. 5 cappn capture positive function enable. this bit enables the positive edge capture for pca module n when set to 1. 4 capnn capture negative function enable. this bit enables the negative edge capture for pca module n when set to 1. 3matn match function enable. this bit enables the match function for pca module n when set to 1. when enabled, matches of the pca counter with a module's capture/compare register cause the ccfn bit in pca0md register to be set to logic 1. 2togn toggle function enable. this bit enables the toggle function for pca module n when set to 1. when enabled, matches of the pca counter with a module's capture/compare register cause the logic level on the cexn pin to toggle . if the pwmn bit is also set to logic 1, the module oper- ates in frequency output mode. 1pwmn pulse width modulation mode enable. this bit enables the pwm function for pca module n when set to 1. when enabled, a pulse width modulated signal is output on the cexn pin. 8 to 11-bit pwm is used if pwm16n is cleared; 16-bit mode is used if pwm1 6n is set to logic 1. if the togn bit is also set, the module operates in frequency output mode. 0eccfn capture/compare flag interrupt enable. this bit sets the masking of the ca pture/compare flag (ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag interrupt request when ccfn is set. note: when the wdte bit is set to 1, the pca0cpm4 register cannot be modified, and module 4 acts as the watchdog timer. to change the contents of the pca0cpm4 register or the function of module 4, the watchdog timer must be disabled. c8051t620/621/320/321/322/323 280 rev. 1.1 sfr address = 0xf9 sfr address = 0xfa sfr definition 29.5. pca0l: pca counter/timer low byte bit76543210 name pca0[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0[7:0] pca counter/timer low byte. the pca0l register holds the low byte (lsb) of the 16-bit pca counter/timer. note: when the wdte bit is set to 1, the pca0l register cannot be modified by software. to change the contents of the pca0l register, the watchdog timer must first be disabled. sfr definition 29.6. pca0h: pca counter/timer high byte bit76543210 name pca0[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0[15:8] pca counter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca counter/timer. reads of this register will read the contents of a ?snapsh ot? register, whose contents are updated only when the contents of pca0l are read (see section 29.1). note: when the wdte bit is set to 1, the pca0h register cannot be modified by software. to change the contents of the pca0h register, the watchdog timer must first be disabled. rev. 1.1 281 c8051t620/621/320/321/322/323 sfr addresses: 0xfb (n = 0), 0xe9 (n = 1) , 0xeb (n = 2), 0xed (n = 3), 0xfd (n = 4) sfr addresses: 0xfc (n = 0), 0xea (n = 1), 0xec (n = 2), 0xee (n = 3), 0xfe (n = 4) sfr definition 29.7. pca0cpln : pca capture module low byte bit76543210 name pca0cpn[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0cpn[7:0] pca capture module low byte. the pca0cpln register holds the low byte (lsb) of the 16-bit capture module n. this register address also allows acce ss to the low byte of the corresponding pca channel?s auto-reload value for 9, 10, or 11-bit pwm mode. the arsel bit in register pca0pwm controls which register is accessed. note: a write to this register will clear the module?s ecomn bit to a 0. sfr definition 29.8. pca0cphn: pca capture module high byte bit76543210 name pca0cpn[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0cpn[15:8] pca capture module high byte. the pca0cphn register holds the high byte (msb) of the 16-bit capture module n. this register address also allows access to the high byte of the corresponding pca channel?s auto-reload value for 9, 10, or 11-bit pwm mode. the arsel bit in register pca0pwm controls which register is accessed. note: a write to this register will set the module?s ecomn bit to a 1. c8051t620/621/320/321/322/323 282 rev. 1.1 30. c2 interface c8051t620/621/3 20/321/322/323 devices in clude an on-chip silicon labs 2- wire (c2) debug interface to allow eprom programming and in-system debugging with the production part installed in the end applica- tion. the c2 interface operates using only two pins: a bi-directional data signal (c2d), and a clock input (c2ck). see the c2 interface specificat ion for details on the c2 protocol. 30.1. c2 interface registers the following describes the c2 registers necessary to perform eprom programming functions through the c2 interface. all c2 registers are accessed through the c2 interface as described in the c2 interface spec- ification. c2 register definition 30.1. c2add: c2 address bit76543210 name c2add[7:0] type r/w reset 00000000 bit name function 7:0 c2add[7:0] write: c2 address. selects the target data register for c2 data read and data write commands accord- ing to the following list. address name description 0x00 deviceid selects the device id register (read only) 0x01 revid selects the revision id register (read only) 0x02 devctl selects the c2 device control register 0xdf epctl selects the c2 eprom programming control register 0xbf epdat selects the c2 eprom data register 0xb7 epstat selects the c2 eprom status register 0xaf epaddrh selects th e c2 eprom address high byte register 0xae epaddrl selects the c2 epr om address low byte register 0xa9 crc0 selects the crc0 register 0xaa crc1 selects the crc1 register 0xab crc2 selects the crc2 register 0xac crc3 selects the crc3 register read: c2 status returns status information on t he current programming operation. when the msb (bit 7) is set to 1, a read or write operation is in progress. all other bits can be ignored by the programming tools. rev. 1.1 283 c8051t620/621/320/321/322/323 c2 address: 0x00 c2 address: 0x01 c2 register definition 30. 2. deviceid: c2 device id bit76543210 name deviceid[7:0] type r/w reset 00011000 bit name function 7:0 deviceid[7:0] device id. this read-only register returns the 8-bit device id: 0x18 (c8051t620/621/320/321/322/323). c2 register definition 30. 3. revid: c2 revision id bit76543210 name revid[7:0] type r/w reset varies varies varies varies varies varies varies varies bit name function 7:0 revid[7:0] revision id. this read-only register returns the 8-bit revision id. for example: 0x00 = revision a. c8051t620/621/320/321/322/323 284 rev. 1.1 c2 address: 0x02 c2 address: 0xdf c2 register definition 30.4. devctl: c2 device control bit76543210 name devctl[7:0] type r/w reset 00000000 bit name function 7:0 devctl[7:0] device control register. this register is used to halt the device for eprom operations via the c2 interface. refer to the eprom chapte r for more information. c2 register definition 30.5. epctl: eprom programming control register bit76543210 name epctl[7:0] type r/w reset 00000000 bit name function 7:0 epctl[7:0] eprom programming control register. this register is used to enable eprom programming via the c2 interface. refer to the eprom chapter for more information. rev. 1.1 285 c8051t620/621/320/321/322/323 c2 address: 0xbf c2 address: 0xb7 c2 register definition 30. 6. epdat: c2 eprom data bit76543210 name epdat[7:0] type r/w reset 00000000 bit name function 7:0 epdat[7:0] c2 eprom data register. this register is used to pass eprom data during c2 eprom operations. c2 register definition 30.7. epstat: c2 eprom status bit76543210 name wrlock rdlock error type rrrrrrrr reset 00000000 bit name function 7wrlock write lock indicator. set to '1' if epaddr currently points to a write-locked address. 6 rdlock read lock indicator. set to '1' if epaddr currently points to a read-locked address. 5:1 unused unused. read = 00000b; write = don?t care. 0error error indicator. set to '1' if last eprom read or write operation failed du e to a security restriction. c8051t620/621/320/321/322/323 286 rev. 1.1 c2 address: 0xaf c2 address: 0xae c2 register definition 30.8. ep addrh: c2 eprom address high byte bit76543210 name epaddr[15:8] type r/w reset 00000000 bit name function 7:0 epaddr[15:8] c2 eprom address high byte. this register is used to set the eprom address location during c2 eprom oper- ations. c2 register definition 30.9. ep addrl: c2 eprom address low byte bit76543210 name epaddr[7:0] type r/w reset 00000000 bit name function 7:0 epaddr[15:8] c2 eprom address low byte. this register is used to set the eprom address location during c2 eprom oper- ations. rev. 1.1 287 c8051t620/621/320/321/322/323 c2 address: 0xa9 c2 address: 0xaa c2 register definition 30.10. crc0: crc byte 0 bit76543210 name crc[7:0] type r/w reset 00000000 bit name function 7:0 crc[7:0] crc byte 0. a write to this register in itiates a 16-bit crc of one 256-byte block of eprom mem- ory. the byte written to crc0 is the uppe r byte of the 16-bit address where the crc will begin. the lower byte of the beginnin g address is always 0x00. when complete, the 16-bit result will be available in crc1 (msb) and crc0 (lsb). see section ?18.4. program memory crc? on page 110. c2 register definition 30.11. crc1: crc byte 1 bit76543210 name crc[15:8] type r/w reset 00000000 bit name function 7:0 crc[15:8] crc byte 1. a write to this regist er initiates a 32-bit crc on the entire program memory space. the crc begins at address 0x0000. when co mplete, the 32-bit result is stored in crc3 (msb), crc2, crc1, and crc0 (lsb). see section ?18.4. program memory crc? on page 110. c8051t620/621/320/321/322/323 288 rev. 1.1 c2 address: 0xab c2 address: 0xac c2 register definition 30.12. crc2: crc byte 2 bit76543210 name crc[23:16] type r/w reset 00000000 bit name function 7:0 crc[23:16] crc byte 2. see section ?18.4. program memory crc? on page 110. c2 register definition 30.13. crc3: crc byte 3 bit76543210 name crc[31:24] type r/w reset 00000000 bit name function 7:0 crc[31:24] crc byte 3. see section ?18.4. program memory crc? on page 110. rev. 1.1 289 c8051t620/621/320/321/322/323 30.2. c2 pin sharing the c2 protocol allows the c2 pins to be shared wi th user functions so that in-system debugging and eprom programming functions may be performed. this is possible because c2 communication is typi- cally performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface can safely ?borrow? the c2ck (normally rst) and c2d pins. in most applications, external resistors are required to isolate c2 interface traffic from the user application when performing debug functions. these external resi stors are not necessary for production boards. a typ- ical isolation configuration is shown in figure 30.1. figure 30.1. typical c2 pin sharing the configuration in figure 30.1 assumes the following: 1. the user input (b) cannot change stat e while the target device is halted. 2. the rst pin on the target device is used as an input only. additional resistors may be necessary depending on the specific application. c2d c2ck rst (a) input (b) output (c) c2 interface master c8051t620/621/320/321/322/323 290 rev. 1.1 d ocument c hange l ist revision 0.1 to revision 1.0 ? updated ?electrical characteristics? on page 33. revision 1.0 to revision 1.1 ? updated reset values for po wer, emi0cf, vdm0cn, amx0p, cpt0mx, and cpt1mx sfrs. ? updated figure 21.1 on page 122. rev. 1.1 291 c8051t620/621/320/321/322/323 n otes : c8051t620/621/320/321/322/323 292 rev. 1.1 c ontact i nformation silicon laboratories inc. silicon laboratories inc. ? 400 west cesar chavez ? austin, tx 78701 ? tel: 1+(512) 416-8500 ? fax: 1+(512) 416-9669 ? toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: ? https://www.silabs.com/support/pages/contacttechnicalsupport.aspx ? and register to submit a technical support request. silicon laboratories and silicon labs ar e trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademark s or registered trademarks of their respective holders the information in this document is believed to be accurate in al l respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no re sponsibility for errors and omissions, and disclaims responsibi lity for any consequen ces resulting from the use of information included herein. additionally, silicon laboratories assume s no responsibility for the fun ction- ing of undescribed features or parameters. silicon laboratories reserves the right to make changes wi thout further notice. sili con laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does silicon laboratories assu me any liability arising out of the applicati on or use of any product or circuit, and specifi cally disclaims any and all liability, including without limitation consequential or incident al damages. silicon laboratories product s are not designed, intended, or authorized for use in applications in tended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a si tuation where personal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. |
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